openwrt/target/linux/ramips/dts/mt7621_xiaomi_mir3g-v2.dts

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/dts-v1/;

#include "mt7621.dtsi"

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>

/ {
	compatible = "xiaomi,mir3g-v2", "mediatek,mt7621-soc";
	model = "Xiaomi Mi Router 3G v2";

	aliases {
		led-boot = &led_status_yellow;
		led-failsafe = &led_status_yellow;
		led-running = &led_status_blue;
		led-upgrade = &led_status_yellow;
	};

	chosen {
		bootargs = "console=ttyS0,115200n8";
	};

	leds {
		compatible = "gpio-leds";

		led_status_blue: status_blue {
			label = "mir3gv2:blue:status";
			gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
		};

		led_status_yellow: status_yellow {
			label = "mir3gv2:yellow:status";
			gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
		};
	};

	keys {
		compatible = "gpio-keys";

		reset {
			label = "reset";
			gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_RESTART>;
		};
	};
};

&spi0 {
	status = "okay";

	m25p80@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <80000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "u-boot";
				reg = <0x0 0x30000>;
				read-only;
			};

			partition@30000 {
				label = "u-boot-env";
				reg = <0x30000 0x10000>;
				read-only;
			};

			partition@40000 {
				label = "Bdata";
				reg = <0x40000 0x10000>;
				read-only;
			};

			factory: partition@50000 {
				label = "factory";
				reg = <0x50000 0x10000>;
				read-only;
			};

			partition@60000 {
				label = "crash";
				reg = <0x60000 0x10000>;
				read-only;
			};

			partition@70000 {
				label = "cfg_bak";
				reg = <0x70000 0x10000>;
				read-only;
			};

			partition@80000 {
				label = "overlay";
				reg = <0x80000 0x100000>;
				read-only;
			};

			firmware: partition@180000 {
				compatible = "denx,uimage";
				label = "firmware";
				reg = <0x180000 0xe80000>;
			};
		};
	};
};

&pcie {
	status = "okay";
};

&pcie0 {
	wifi@0,0 {
		compatible = "pci14c3,7662";
		reg = <0x0000 0 0 0 0>;
		mediatek,mtd-eeprom = <&factory 0x8000>;
		ieee80211-freq-limit = <5000000 6000000>;
	};
};

&pcie1 {
	wifi@0,0 {
		compatible = "pci14c3,7603";
		reg = <0x0000 0 0 0 0>;
		mediatek,mtd-eeprom = <&factory 0x0000>;
		ieee80211-freq-limit = <2400000 2500000>;
	};
};

&ethernet {
	mtd-mac-address = <&factory 0xe000>;
	mediatek,portmap = "lllwl";
};

&state_default {
	gpio {
		ralink,group = "jtag", "uart2", "uart3", "wdt";
		ralink,function = "gpio";
	};
};