mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-27 01:11:14 +00:00
85c5c9aa68
These are not referenced. Signed-off-by: Rosen Penev <rosenp@gmail.com>
128 lines
2.1 KiB
Plaintext
128 lines
2.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
|
|
|
#include "ar9344.dtsi"
|
|
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/input/input.h>
|
|
|
|
/ {
|
|
aliases {
|
|
led-boot = &led_system;
|
|
led-failsafe = &led_system;
|
|
led-running = &led_system;
|
|
led-upgrade = &led_system;
|
|
};
|
|
|
|
leds: leds {
|
|
compatible = "gpio-leds";
|
|
|
|
wlan2g {
|
|
label = "green:wlan2g";
|
|
gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
|
|
linux,default-trigger = "phy0tpt";
|
|
};
|
|
|
|
led_system: system {
|
|
label = "green:system";
|
|
gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
|
|
default-state = "on";
|
|
};
|
|
|
|
qss {
|
|
label = "green:qss";
|
|
gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
|
|
};
|
|
};
|
|
|
|
ath9k-leds {
|
|
compatible = "gpio-leds";
|
|
|
|
wlan5g {
|
|
label = "green:wlan5g";
|
|
gpios = <&ath9k 0 GPIO_ACTIVE_LOW>;
|
|
linux,default-trigger = "phy1tpt";
|
|
};
|
|
};
|
|
|
|
keys {
|
|
compatible = "gpio-keys";
|
|
|
|
reset {
|
|
linux,code = <KEY_RESTART>;
|
|
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
|
|
debounce-interval = <60>;
|
|
};
|
|
|
|
wifi {
|
|
linux,code = <KEY_RFKILL>;
|
|
linux,input-type = <EV_SW>;
|
|
gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
|
|
debounce-interval = <60>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&ref {
|
|
clock-frequency = <40000000>;
|
|
};
|
|
|
|
&spi {
|
|
status = "okay";
|
|
|
|
flash@0 {
|
|
compatible = "jedec,spi-nor";
|
|
reg = <0>;
|
|
spi-max-frequency = <33000000>;
|
|
|
|
partitions {
|
|
compatible = "fixed-partitions";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
uboot: partition@0 {
|
|
label = "u-boot";
|
|
reg = <0x000000 0x020000>;
|
|
read-only;
|
|
|
|
nvmem-layout {
|
|
compatible = "fixed-layout";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
macaddr_uboot_1fc00: macaddr@1fc00 {
|
|
compatible = "mac-base";
|
|
reg = <0x1fc00 0x6>;
|
|
#nvmem-cell-cells = <1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
partition@20000 {
|
|
compatible = "tplink,firmware";
|
|
label = "firmware";
|
|
reg = <0x020000 0x7d0000>;
|
|
};
|
|
|
|
partition@7f0000 {
|
|
label = "art";
|
|
reg = <0x7f0000 0x010000>;
|
|
read-only;
|
|
|
|
nvmem-layout {
|
|
compatible = "fixed-layout";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
cal_art_1000: cal@1000 {
|
|
reg = <0x1000 0x440>;
|
|
};
|
|
|
|
cal_art_5000: cal@5000 {
|
|
reg = <0x5000 0x440>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|