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0e5d67d483
Backport kernel patches for LS1043A Rev1.1 support from upstream, patchwork, and SDK. And update to latest u-boot to support LS1043A Rev1.1. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
52 lines
2.1 KiB
Diff
52 lines
2.1 KiB
Diff
From 60eedf7a9512683e2a8a998863cc5942e9dbdae5 Mon Sep 17 00:00:00 2001
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From: Minghuan Lian <Minghuan.Lian@nxp.com>
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Date: Tue, 17 Jan 2017 17:32:39 +0800
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Subject: [PATCH 08/13] arm64: dts: ls1043a: share all MSIs
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Cherry-pick patchwork patch.
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In order to maximize the use of MSI, a PCIe controller will share
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all MSI controllers. The patch changes "msi-parent" to refer to all
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MSI controller dts nodes.
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Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
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Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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---
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arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 6 +++---
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1 file changed, 3 insertions(+), 3 deletions(-)
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diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
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index e51a6cb..92d18c5 100644
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
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@@ -1033,7 +1033,7 @@
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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- msi-parent = <&msi1>;
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+ msi-parent = <&msi1>, <&msi2>, <&msi3>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
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@@ -1058,7 +1058,7 @@
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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- msi-parent = <&msi2>;
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+ msi-parent = <&msi1>, <&msi2>, <&msi3>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
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@@ -1083,7 +1083,7 @@
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bus-range = <0x0 0xff>;
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ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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- msi-parent = <&msi3>;
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+ msi-parent = <&msi1>, <&msi2>, <&msi3>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
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--
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2.1.0.27.g96db324
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