openwrt/target/linux/siflower/dts/sf21h8898_bananapi_bpi-rv2.dtsi
Chuanhong Guo b8a8bf53e9 siflower: sf21: add support for Bananapi BPI-RV2
Specification:
 - Siflower SF21H8898
 - 512MB DDR3, 128MB SPI-NAND and 16MB SPI-NOR
 - 5x Gigabit ports (SF23P1240 QSGMII PHY and SF23P1211F RGMII PHY)
 - 1x 2.5G port (Airoha EN8811H PHY)
 - M.2 Key B slot with USB2.0, PCIEx1 and a NanoSIM card slot
 - MiniPCIe slot with USB2.0 and PCIEx1
 - 1x USB2.0 port through USB Hub
 - PCF8563-compatible RTC

The SoC can only boot from SPI0. Two SPI flash chipselects are connected
to GPIO5 (SPI0 CS) and GPIO36 through a 2x2 jumper. It boots from
SPI-NOR or SPI-NAND depending on how the jumpers are connected.

The firmware can be flashed using U-boot web recovery from Siflower
vendor U-boot.

Link: https://github.com/openwrt/openwrt/pull/17115
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
2025-02-05 11:08:37 +08:00

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3.6 KiB
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/dts-v1/;
#include "sf21h8898.dtsi"
/ {
chosen {
bootargs = "root=/dev/fit0 rootwait";
stdout-path = "serial1:115200n8";
rootdisk = <&rootdisk>;
};
memory@20000000 {
device_type = "memory";
reg = <0x0 0x20000000 0x0 0x20000000>;
};
usb_vbus: regulator@0 {
compatible = "regulator-fixed";
regulator-name = "usb_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio 37 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&spi0_pins {
pinctrl-single,pins = <
SPI0_TXD FUNC_MODE0
SPI0_RXD FUNC_MODE0
SPI0_CLK FUNC_MODE0
SPI0_HOLD FUNC_MODE0
SPI0_WP FUNC_MODE0
>;
};
&watchdog {
status = "okay";
};
&uart1 {
status = "okay";
};
&iomux {
rtc_int_gpio: rtc-int-pins {
pinctrl-single,pins = <PHY_INT GPIO_MODE>;
// disable internal bias as it's externally (and weakly) pulled up
pinctrl-single,bias-pullup = <0 SW_PU 0 SW_PU>;
pinctrl-single,bias-pulldown = <0 SW_PD 0 SW_PD>;
};
};
&i2c0 {
status = "okay";
rtc: rtc@51 {
compatible = "analogtek,at8563", "nxp,pcf8563";
reg = <0x51>;
#clock-cells = <0>;
interrupts-extended = <&gpio 40 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&rtc_int_gpio>;
};
};
&xgmac0 {
status = "okay";
phy-handle = <&phy1>;
nvmem-cells = <&macaddr_factory_0 0>;
nvmem-cell-names = "mac-address";
};
&xgmac1 {
status = "okay";
phy-handle = <&phy2>;
nvmem-cells = <&macaddr_factory_0 0>;
nvmem-cell-names = "mac-address";
};
&xgmac2 {
status = "okay";
phy-handle = <&phy3>;
nvmem-cells = <&macaddr_factory_0 0>;
nvmem-cell-names = "mac-address";
};
&xgmac3 {
status = "okay";
phy-handle = <&phy4>;
nvmem-cells = <&macaddr_factory_0 0>;
nvmem-cell-names = "mac-address";
};
&xgmac4 {
status = "okay";
phy-handle = <&phy15>;
nvmem-cells = <&macaddr_factory_0 1>;
nvmem-cell-names = "mac-address";
mac-address-increment = <1>;
/delete-property/ pinctrl-0;
};
&xgmac5 {
status = "okay";
tx-internal-delay-ps = <2499>;
rx-internal-delay-ps = <1519>;
phy-mode = "rgmii-txid";
phy-handle = <&phy6>;
nvmem-cells = <&macaddr_factory_0 0>;
nvmem-cell-names = "mac-address";
};
&mdio0 {
reset-gpios = <&gpio 30 GPIO_ACTIVE_LOW>;
reset-delay-us = <10000>;
reset-post-delay-us = <100000>;
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1>;
};
phy2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x2>;
};
phy3: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x3>;
};
phy4: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x4>;
};
phy6: ethernet-phy@6 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x6>;
reset-gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <100000>;
};
phy15: ethernet-phy@f {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0xf>;
reset-gpios = <&gpio 39 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <100000>;
};
};
&pcie_phy {
status = "okay";
};
/*
* M.2 Key B slot. Other GPIO pins connected to the slot:
* GPIO0: WAKEUP
* GPIO8: W_DISABLE
* GPIO10: CLKREQ_N
* GPIO38: FULL_CARD_POFF
*/
&pcie0 {
reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
status = "okay";
};
/*
* MiniPCIE slot. Other GPIO pins connected to the slot:
* GPIO11: PEWAKE
* GPIO12: CLKREQ_N
*/
&pcie1 {
reset-gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
status = "okay";
};
&usb_phy {
status = "okay";
};
&usb {
status = "okay";
};
&dpns {
status = "okay";
};
&edma {
status = "okay";
};
&qsgmii_pcs {
status = "okay";
};
&sgmii_pcs {
status = "okay";
};