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c057db94f8
Siflower SF21A6826/SF21H8898 are a family of RISC-V SoCs with: * Quad-core T-Head C908 (1.125G for SF21A6826, 1.25G for SF21H8898) * DDR3/DDR4 memory controller * 1 QSGMII 4x1G * 1 SGMII/2500Base-X 2.5G * 1 additional RGMII on SF21H8898 * Network offloading engine for L2 switching and L3 NAT * 2 PCIE Gen2 lanes, operating in either one PCIE Gen2x2 or two PCIE Gen2x1 mode * 1 USB2.0 Link: https://github.com/openwrt/openwrt/pull/17115 Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
40 lines
1.2 KiB
Plaintext
40 lines
1.2 KiB
Plaintext
#include "sf21.dtsi"
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/ {
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compatible = "siflower,sf21h8898";
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soc {
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xgmac5: ethernet@8014000 {
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compatible = "siflower,sf21-xgmac";
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reg = <0x0 0x8014000 0x0 0x4000>;
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dmas = <&edma>;
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ethsys = <ðsys>;
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clocks = <&topcrm CLK_SERDES_CSR>, <&topcrm CLK_GMAC_BYP_REF>;
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clock-names = "csr", "rgmii";
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phy-mode = "rgmii";
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii_pins>;
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interrupts = <5 IRQ_TYPE_LEVEL_HIGH>, <25 IRQ_TYPE_LEVEL_HIGH>, <31 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "sbd", "lpi", "pmt";
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status = "disabled";
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};
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};
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};
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&cpus {
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timebase-frequency = <1250000000>;
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};
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&topcrm {
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assigned-clocks = <&topcrm CLK_CMNPLL_VCO>, <&topcrm CLK_PIC>, <&topcrm CLK_AXI>,
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<&topcrm CLK_AHB>, <&topcrm CLK_APB>, <&topcrm CLK_UART>,
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<&topcrm CLK_IRAM>, <&topcrm CLK_NPU>, <&topcrm CLK_ETHTSU>,
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<&topcrm CLK_GMAC_BYP_REF>, <&topcrm CLK_USB>, <&topcrm CLK_USBPHY>,
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<&topcrm CLK_SERDES_CSR>, <&topcrm CLK_CRYPT_CSR>, <&topcrm CLK_CRYPT_APP>,
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<&topcrm CLK_IROM>;
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assigned-clock-rates = <2500000000>, <416666666>, <416666666>,
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<250000000>, <178571428>, <89285714>,
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<416666666>, <416666666>, <89285714>,
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<250000000>, <250000000>, <50000000>,
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<89285714>, <73529411>, <312500000>,
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<312500000>;
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};
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