Commit Graph

10 Commits

Author SHA1 Message Date
Adrian Schmutzler
fcb920ffe7 ath79: Consistently label art partition with lower case
This patch harmonizes the label and alias for art partitions
across ath79. Since lower case seems to be more frequent, use that
consistently.

Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
2019-06-10 11:25:41 +02:00
Petr Štetiar
0d23fd2ab2 treewide: dts: Remove default-state=off property from all gpio LED nodes
>From the Documentation/devicetree/bindings/leds/common.txt:

- default-state : The initial state of the LED. Valid values are "on", "off",
  and "keep". If the LED is already on or off and the default-state property is
  set the to same value, then no glitch should be produced where the LED
  momentarily turns off (or on). The "keep" setting will keep the LED at
  whatever its current state is, without producing a glitch.  The default is
  off if this property is not present.

So setting the default-state of the LEDs to `off` is redundant as `off`
is default LED state anyway. We should remove it as almost every new
PR/patch submission contains this property by default which seems to be
just copy&paste from some DTS file already present in the tree.

Signed-off-by: Petr Štetiar <ynezz@true.cz>
2018-12-17 08:16:28 +01:00
Petr Štetiar
bc41fb7efe ath79: Define firmware partition format to all boards where applicable
Parsing "firmware" partition (to create kernel + rootfs) was implemented
using OpenWrt downstream code enabled by CONFIG_MTD_SPLIT_FIRMWARE. With
recent upstream mtd changes we can do it in a more clean way for DTS
targets. It just requires adding a proper "compatible" string to the
"firmware" partition node.

Signed-off-by: Petr Štetiar <ynezz@true.cz>
2018-12-06 13:28:22 +01:00
David Bauer
6555612783 ath79: fix PLL settings for QCA955x
This adds PLL settings for the ethernet ports of the TP-Link TL-WR1043
v2/v3 and the Openmesh OM5P-AC-v2.

We also change the PLL-settings in the qca9557.dtsi to match the ones
used as default on the ar71xx target.

As of 4b9680f138 those devices have broken ethernet ports as the default
PLL settings defined in the QCA9557.dtsi are applied which are off for
those devices.

Signed-off-by: David Bauer <mail@david-bauer.net>
2018-08-09 17:24:39 +01:00
Mathias Kresin
55ff2951ea ath79: fix dts warnings
Fix all issues found by the devicetree compiler like wrong address/size
cells as well as wrong/missing/superfluous unit addresses.

Signed-off-by: Mathias Kresin <dev@kresin.me>
2018-08-08 08:11:11 +02:00
Mathias Kresin
a8ad7b6efa ath79: fix compatible strings
Use only the jedec,spi-nor compatible string. Everything else either
never worked or is only support to keep compatibility.

Signed-off-by: Mathias Kresin <dev@kresin.me>
2018-08-08 07:24:22 +02:00
Chuanhong Guo
c463320812 ath79: Remove all memory nodes defined in dts
This target can automatically detect the correct memory size and we've
been using it for long in ar71xx.

Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
2018-06-28 18:39:57 +02:00
Johann Neuhauser
b8562f168b ath79: qca95xx: add new intc2, correct intc3 and add second pcie on qca9557
Signed-off-by: Johann Neuhauser <johann@it-neuhauser.de>
2018-06-20 11:12:00 +02:00
John Crispin
c49ae68cba ath79: fix qm5p-ac-v2 dts file
Signed-off-by: John Crispin <john@phrozen.org>
2018-06-18 23:23:30 +02:00
Mathias Kresin
0ff5785c5d ath79: fix dts files
Add the SoC compatible to the individual dts files. Rename the dts files
to match the common pattern.

Remove dts files wich aren't used and no image in ar71xx exists.

Signed-off-by: Mathias Kresin <dev@kresin.me>
2018-05-17 07:40:19 +02:00