Commit Graph

253 Commits

Author SHA1 Message Date
Raylynn Knight
ee4a765090 realtek: add support for ZyXEL GS1900-24E
The ZyXEL GS1900-24E is a 24 port gigabit switch similar to other GS1900
switches.

Specifications
--------------
* Device:    ZyXEL GS1900-24E
* SoC:       Realtek RTL8382M 500 MHz MIPS 4KEc
* Flash:     16 MiB Macronix MX25L12835F
* RAM:       128 MiB DDR2 SDRAM Nanya NT5TU128M8GE
* Ethernet:  24x 10/100/1000 Mbps
* LEDs:      1 PWR LED (green, not configurable)
             1 SYS LED (green, configurable)
             24 ethernet port link/activity LEDs (green, SoC controlled)
* Buttons:   1 "RESET" button on front panel
* Switch:    1 Power switch on rear of device
* Power      120-240V AC C13
* UART:      1 serial header (JP2) with populated standard pin connector on
             the left side of the PCB.
             Pinout (front to back):
             + Pin 1 - VCC marked with white dot
             + Pin 2 - RX
             + Pin 3 - TX
             + PIn 4 - GND

Serial connection parameters:  115200 8N1.

Installation
------------

OEM upgrade method:

* Log in to OEM management web interface
* Navigate to Maintenance > Firmware
* Select the HTTP radio button
* Select the Active radio button
* Use the browse button to locate the
realtek-rtl838x-zyxel_gs1900-24e-initramfs-kernel.bin
file and select open so File Path is updated with filename.
* Select the Apply button. Screen will display "Prepare
for firmware upgrade ...".
*Wait until screen shows "Do you really want to reboot?"
then select the OK button
* Once OpenWrt has booted, scp the sysupgrade image to /tmp and flash it:
   > sysupgrade -n /tmp/realtek-rtl838x-zyxel_gs1900-24e-squashfs-sysupgrade.bin
   it may be necessary to restart the network (/etc/init.d/network restart) on
   the running initramfs image.

U-Boot TFTP method:

* Configure your client with a static 192.168.1.x IP (e.g. 192.168.1.10).
* Set up a TFTP server on your client and make it serve the initramfs image.
* Connect serial, power up the switch, interrupt U-boot by hitting the
  space bar, and enable the network:
   > rtk network on
* Since the GS1900-24E is a dual-partition device, you want to keep the OEM
  firmware on the backup partition for the time being. OpenWrt can only boot
  from the first partition anyway (hardcoded in the DTS). To make sure we are
  manipulating the first partition, issue the following commands:
  > setsys bootpartition 0
  > savesys
* Download the image onto the device and boot from it:
   > tftpboot 0x84f00000 192.168.1.10:openwrt-realtek-rtl838x-zyxel_gs1900-24e-initramfs-kernel.bin
   > bootm
* Once OpenWrt has booted, scp the sysupgrade image to /tmp and flash it:
   > sysupgrade -n /tmp/openwrt-realtek-rtl838x-zyxel_gs1900-24e-squashfs-sysupgrade.bin
   it may be necessary to restart the network (/etc/init.d/network restart) on
   the running initramfs image.

Signed-off-by: Raylynn Knight <rayknight@me.com>
(cherry picked from commit b515ad10a6)
2022-06-06 11:05:29 +02:00
Raylynn Knight
a11c3cde27 realtek: add support for ZyXEL GS1900-16
The ZyXEL GS1900-16 is a 16 port gigabit switch similar to other GS1900 switches.

Specifications
--------------
* Device:    ZyXEL GS1900-16
* SoC:       Realtek RTL8382M 500 MHz MIPS 4KEc
* Flash:     16 MiB Macronix MX25L12835F
* RAM:       128 MiB DDR2 SDRAM Nanya NT5TU128M8HE
* Ethernet:  16x 10/100/1000 Mbps
* LEDs:      1 PWR LED (green, not configurable)
             1 SYS LED (green, configurable)
             16 ethernet port link/activity LEDs (green, SoC controlled)
* Buttons:   1 "RESET" button on front panel
* Power      120-240V AC C13
* UART:      1 serial header (J12) with populated standard pin connector on
             the right back of the PCB.
             Pinout (front to back):
             + Pin 1 - VCC marked with white dot
             + Pin 2 - RX
             + Pin 3 - TX
             + PIn 4 - GND

Serial connection parameters:  115200 8N1.

Installation
------------

OEM upgrade method:

* Log in to OEM management web interface
* Navigate to Maintenance > Firmware
* Select the HTTP radio button
* Select the Active radio button
* Use the browse button to locate the
realtek-generic-zyxel_gs1900-16-initramfs-kernel.bin
file amd select open so File Path is update with filename.
* Select the Apply button. Screen will display "Prepare
for firmware upgrade ...".
*Wait until screen shows "Do you really want to reboot?"
then select the OK button
* Once OpenWrt has booted, scp the sysupgrade image to /tmp and flash it:
   > sysupgrade -n /tmp/realtek-generic-zyxel_gs1900-16-squashfs-sysupgrade.bin
   it may be necessary to restart the network (/etc/init.d/network restart) on
   the running initramfs image.

U-Boot TFTP method:

* Configure your client with a static 192.168.1.x IP (e.g. 192.168.1.10).
* Set up a TFTP server on your client and make it serve the initramfs image.
* Connect serial, power up the switch, interrupt U-boot by hitting the
  space bar, and enable the network:
   > rtk network on
* Since the GS1900-16 is a dual-partition device, you want to keep the OEM
  firmware on the backup partition for the time being. OpenWrt can only boot
  from the first partition anyway (hardcoded in the DTS). To make sure we are
  manipulating the first partition, issue the following commands:
  > setsys bootpartition 0
  > savesys
* Download the image onto the device and boot from it:
   > tftpboot 0x84f00000 192.168.1.10:openwrt-realtek-generic-zyxel_gs1900-16-initramfs-kernel.bin
   > bootm
* Once OpenWrt has booted, scp the sysupgrade image to /tmp and flash it:
   > sysupgrade -n /tmp/openwrt-realtek-generic-zyxel_gs1900-16-squashfs-sysupgrade.bin
   it may be necessary to restart the network (/etc/init.d/network restart) on
   the running initramfs image.

Signed-off-by: Raylynn Knight <rayknight@me.com>
[removed duplicate patch title, align RAM specification]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit 580723e86a)
2022-05-17 21:14:46 +02:00
John Audia
e0aaecdbb8 kernel: bump 5.10 to 5.10.114
All patches automatically rebased.

Build system: x86_64
Build-tested: bcm2711/RPi4B
Run-tested: bcm2711/RPi4B

Signed-off-by: John Audia <therealgraysky@proton.me>
(cherry picked from commit 8592df67f4)
2022-05-17 20:50:27 +02:00
Birger Koblitz
a374a959b9 realtek: do not reset SerDes on link change
Do not reset the RTL930x SerDes on link changes, instead set up
the SDS with internal PHYs for the SFP+ ports only.
This fixes the 8 1GBit ports on the Zyxel XGS1250 which
do not work without this patch.

A complete SerDes reset was performed on all SerDes links. For copper
1Gbit ports, this is commonly a single XGMII link to an RTL8218D. There
is however no support for setting up the XGMII link on RTL9300/RTL9310,
thereby wiping the (RX/TX) setup done by u-boot and breaking the 1GBit
ports. No SerDes reset should be done for these links.

The handling of SGMII/HiSGMII, 1000BX or 10GR links is actually entirely
different. All these modes need to be suitably RX calibrated and the
pre- main and post- amplifiers set up properly for TX.

The 10GBit SFP+ fiber links are recalibrated instead of reset, which
e.g. is necessary when someone pulls a module out and puts another in.
This makes swapping out 10GBit fiber modules possible. 1GBit modules are
not yet supported, nor any modules with an internal phy.

Tested-by: Stijn Segers <foss@volatilesystems.org>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
[rewrite commit message based on discussion]
Link: http://lists.infradead.org/pipermail/openwrt-devel/2022-May/038623.html
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit d1b824650f)
2022-05-14 21:26:14 +02:00
Birger Koblitz
7b4702afef realtek: Trap all frames with switch as destination to CPU-port
This fixes a bug where frames sent to the switch itself were
flooded to all ports unless the MAC address of the CPU-port
was learned otherwise.

Tested-by: Wenli Looi <wlooi@ucalgary.ca>
Tested-by: Bjørn Mork <bjorn@mork.no>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
[fix code formatting]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit 98bb26f9f7)
2022-05-14 21:26:14 +02:00
Martin Kennedy
d60b3bf890 realtek: add ZyXEL GS1900-24HP v1 support
The ZyXEL GS1900-24HP v1 is a 24 port PoE switch with two SFP ports,
similar to the other GS1900 switches.

Specifications
--------------
* Device:    ZyXEL GS1900-24HP v1
* SoC:       Realtek RTL8382M 500 MHz MIPS 4KEc
* Flash:     16 MiB
* RAM:       Winbond W9751G8KB-25 64 MiB DDR2 SDRAM
* Ethernet:  24x 10/100/1000 Mbps, 2x SFP 100/1000 Mbps
* LEDs:
  * 1 PWR LED (green, not configurable)
  * 1 SYS LED (green, configurable)
  * 24 ethernet port link/activity LEDs (green, SoC controlled)
  * 24 ethernet port PoE status LEDs
  * 2 SFP status/activity LEDs (green, SoC controlled)
* Buttons:
  * 1 "RESET" button on front panel (soft reset)
  * 1 button ('SW1') behind right hex grate (hardwired power-off)
* PoE:
  * Management MCU: ST Micro ST32F100 Microcontroller
  * 6 BCM59111 PSE chips
  * 170W power budget
* Power:     120-240V AC C13
* UART:      Internal populated 10-pin header ('J5') providing RS232;
             connected to SoC UART through a TI or SIPEX 3232C for voltage
             level shifting.

* 'J5' RS232 Pinout (dot as pin 1):
  2) SoC RXD
  3) GND
  10) SoC TXD

Serial connection parameters: 115200 8N1.

Installation
------------

OEM upgrade method:

* Log in to OEM management web interface

* Navigate to Maintenance > Firmware > Management

* If "Active Image" has the first option selected, OpenWrt will need to be
  flashed to the "Active" partition. If the second option is selected,
  OpenWrt will need to be flashed to the "Backup" partition.

* Navigate to Maintenance > Firmware > Upload

* Upload the openwrt-realtek-rtl838x-zyxel_gs1900-24hp-v1-initramfs-kernel.bin
  file by your preferred method to the previously determined partition.
  When prompted, select to boot from the newly flashed image, and reboot
  the switch.

* Once OpenWrt has booted, scp the sysupgrade image to /tmp and flash it:

  > sysupgrade /tmp/openwrt-realtek-rtl838x-zyxel_gs1900-24hp-v1-squashfs-sysupgrade.bin

U-Boot TFTP method:

* Configure your client with a static 192.168.1.x IP (e.g. 192.168.1.10).

* Set up a TFTP server on your client and make it serve the initramfs
  image.

* Connect serial, power up the switch, interrupt U-boot by hitting the
  space bar, and enable the network:

  > rtk network on

* Since the GS1900-24HP v1 is a dual-partition device, you want to keep the
  OEM firmware on the backup partition for the time being. OpenWrt can
  only be installed in the first partition anyway (hardcoded in the
  DTS). To ensure we are set to boot from the first partition, issue the
  following commands:

  > setsys bootpartition 0
  > savesys

* Download the image onto the device and boot from it:

  > tftpboot 0x81f00000 192.168.1.10:openwrt-realtek-rtl838x-zyxel_gs1900-24hp-v1-initramfs-kernel.bin
  > bootm

* Once OpenWrt has booted, scp the sysupgrade image to /tmp and flash it:

  > sysupgrade /tmp/openwrt-realtek-rtl838x-zyxel_gs1900-24hp-v1-squashfs-sysupgrade.bin

Signed-off-by: Martin Kennedy <hurricos@gmail.com>
[Add info on PoE hardware to commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
(cherry picked from commit a5ac8ad0ba)
2022-04-19 21:45:46 +02:00
Hauke Mehrtens
b664bb617d realtek: Fix tc default package
The tc package does not exits any more, it was split into tc-tiny,
tc-full and tc-bpf. Include tc-bpf by default into realtek images.

This increases the compressed image size by about 232KBytes.

Tested-by: Stijn Segers <foss@volatilesystems.org>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
(cherry picked from commit 34fb36e165)
2022-03-29 14:28:21 +02:00
Hauke Mehrtens
27fbae4c5a realtek: Use firewall4
The realtek target is not a router, but basic device, see DEVICE_TYPE.
The basic device type does not come with firewall by default, see
include/target.mk for details. The realtek target extended
DEFAULT_PACKAGES manually with firewall.

This changes the defaults to take firewall4 and nftables instead of
firewall and iptables. This also adds the additional package
kmod-nft-offload.

The only difference to the router type is the missing ppp,
ppp-mod-pppoe, dnsmasq and odhcpd-ipv6only package.

This increases the compressed image size by about 422KBytes.

Tested-by: Stijn Segers <foss@volatilesystems.org>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
(cherry picked from commit 469030659c)
2022-03-29 14:28:19 +02:00
Hauke Mehrtens
916f21c63e realtek: Remove dnsmasq and odhcpd-ipv6only from default
Do not include the dnsmasq and odhcpd-ipv6only package by default any
more. These services are not needed on a switch. If someone needs this
it is still possible to use opkg or image builder to add them.

This decreases the compressed image size by about 165KBytes.

Tested-by: Stijn Segers <foss@volatilesystems.org>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
(cherry picked from commit 2acebbdcaa)
2022-03-29 14:28:17 +02:00
John Audia
b04d38a2ea kernel: bump 5.10 to 5.10.106
All patches automatically rebased.

Build system: x86_64
Build-tested: bcm2711/RPi4B, mt7622/RT3200
Run-tested: bcm2711/RPi4B, mt7622/RT3200

Signed-off-by: John Audia <graysky@archlinux.us>
2022-03-19 16:13:58 +01:00
INAGAKI Hiroshi
e83ab243be realtek: add support for Panasonic Switch-M8eG PN28080K
Panasonic Switch-M8eG PN28080K is a 8 + 1 port gigabit switch, based on
RTL8380M.

Specification:

- SoC		: Realtek RTL8380M
- RAM		: DDR3 128 MiB (Winbond W631GG8KB-15)
- Flash		: SPI-NOR 32 MiB (Macronix MX25L25635FMI-10G)
- Ethernet	: 10/100/1000 Mbps x8 + 1
  - port 1-8	: TP, RTL8218B (SoC)
  - port 9	: SFP, RTL8380M (SoC)
- LEDs/Keys	: 7x / 1x
- UART		: RS-232 port on the front panel (connector: RJ-45)
  - 3:TX, 4:GND, 5:GND, 6:RX (pin number: RJ-45)
  - 9600n8
- Power		: 100-240 VAC, 50/60 Hz, 0.5 A
  - Plug	: IEC 60320-C13
- Stock OS	: VxWorks based

Flash instruction using initramfs image:

1.  Prepare the TFTP server with the IP address 192.168.1.111
2.  Rename the OpenWrt initramfs image to "0101A8C0.img" and place it to
    the TFTP directory
3.  Download the official upgrading firmware (ex: pn28080k_v30000.rom)
    and place it to the TFTP directory
4.  Boot M8eG and interrupt the U-Boot with Ctrl + C keys
5.  Execute the following commands and boot with the OpenWrt initramfs
    image

    rtk network on
    tftpboot 0x81000000
    bootm

6.  Backup mtdblock files to the computer by scp or anything and reboot
7.  Interrupt the U-Boot and execute the following commands to re-create
    filesystem in the flash

    ffsmount c:/
    ffsfmt c:/

    this step takes a long time, about ~ 4 mins

8.  Execute the following commands to put the official images to the
    filesystem

    updatert <official image>

    example:

      updatert pn28080k_v30000.rom

    this step takes about ~ 40 secs

9.  Set the environment variables of the U-Boot by the following commands

    setenv loadaddr 0xb4e00000
    setenv bootcmd bootm
    saveenv

10: Download the OpenWrt initramfs image and boot with it

    tftpboot 0x81000000 0101A8C0.img
    bootm

11: On the initramfs image, download the sysupgrade image and perform
    sysupgrade with it

    sysupgrade <imagename>

12: Wait ~ 120 seconds to complete flashing

Note:

- "Switch-M8eG" is a model name, and "PN28080K" is a model number.
  Switch-M8eG has an another (old) model number ("PN28080"), it's not a
  Realtek based hardware.

- Switch-M8eG has a "POWER" LED (Green), but it's not connected to any
  GPIO pin.

- The U-Boot checks the runtime images in the flash when booting and
  fails to execute anything in "bootcmd" variable if the images are not
  exsisting.

- A filesystem is formed in the flash (0x100000-0x1DFFFFF) on the stock
  firmware and it includes the stock images, configuration files and
  checksum files. It's unknown format, can't be managed on the OpenWrt.
  To get the enough space for OpenWrt, move the filesystem to the head
  of "fs_reserved" partition by execution of "ffsfmt" and "updatert".

- On the other devices in the same series of Switch-M8eG PN28080K, the
  INT pin on the PCA9555 is not connected to anywhere.

Back to the stock firmware:

1. Delete "loadaddr" variable and set "bootcmd" to the original value

   on U-Boot:

     setenv loadaddr
     setenv bootcmd 'bootm 0x81000000'

   on OpenWrt:

     fw_setenv loadaddr
     fw_setenv bootcmd 'bootm 0x81000000'

2. Perform reset or reboot

  on U-Boot:

    reset

  on OpenWrt:

    reboot

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Reviewed-by: Sander Vanheule <sander@svanheule.net>
2022-03-13 19:54:57 +01:00
INAGAKI Hiroshi
da1347d6d6 realtek: enable pca953x driver for rtl838x subtarget
The system status LED on Panasonic Switch-M8eG PN28080K is connected to
a PCA9539PW. To use the LED as a status LED of OpenWrt while booting,
enable the pca953x driver and built-in to the kernel.
Also enable CONFIG_GPIO_PCA953X_IRQ to use interrupt via RTL83xx GPIO.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Acked-by: Sander Vanheule <sander@svanheule.net>
2022-03-13 19:54:57 +01:00
Martin Kennedy
d1a8690742 realtek: add ZyXEL GS1900-24 v1 support
The ZyXEL GS1900-24 v1 is a 24 port switch with two SFP ports, similar to
the other GS1900 switches.

Specifications
--------------
* Device:    ZyXEL GS1900-24 v1
* SoC:       Realtek RTL8382M 500 MHz MIPS 4KEc
* Flash:     16 MiB
* RAM:       Winbond W9751G8KB-25 64 MiB DDR2 SDRAM
* Ethernet:  24x 10/100/1000 Mbps, 2x SFP 100/1000 Mbps
* LEDs:
  * 1 PWR LED (green, not configurable)
  * 1 SYS LED (green, configurable)
  * 24 ethernet port link/activity LEDs (green, SoC controlled)
  * 2 SFP status/activity LEDs (green, SoC controlled)
* Buttons:
  * 1 "RESET" button on front panel (soft reset)
  * 1 button ('SW1') behind right hex grate (hardwired power-off)
* Power:     120-240V AC C13
* UART:      Internal populated 10-pin header ('J5') providing RS232;
             connected to SoC UART through a SIPEX 3232EC for voltage
             level shifting.

* 'J5' RS232 Pinout (dot as pin 1):
  2) SoC RXD
  3) GND
  10) SoC TXD

Serial connection parameters: 115200 8N1.

Installation
------------

OEM upgrade method:

* Log in to OEM management web interface

* Navigate to Maintenance > Firmware > Management

* If "Active Image" has the first option selected, OpenWrt will need to be
  flashed to the "Active" partition. If the second option is selected,
  OpenWrt will need to be flashed to the "Backup" partition.

* Navigate to Maintenance > Firmware > Upload

* Upload the openwrt-realtek-rtl838x-zyxel_gs1900-24-v1-initramfs-kernel.bin
  file by your preferred method to the previously determined partition.
  When prompted, select to boot from the newly flashed image, and reboot
  the switch.

* Once OpenWrt has booted, scp the sysupgrade image to /tmp and flash it:

  > sysupgrade /tmp/openwrt-realtek-rtl838x-zyxel_gs1900-24-v1-squashfs-sysupgrade.bin

U-Boot TFTP method:

* Configure your client with a static 192.168.1.x IP (e.g. 192.168.1.10).

* Set up a TFTP server on your client and make it serve the initramfs
  image.

* Connect serial, power up the switch, interrupt U-boot by hitting the
  space bar, and enable the network:

  > rtk network on

> Since the GS1900-24 v1 is a dual-partition device, you want to keep the
  OEM firmware on the backup partition for the time being. OpenWrt can
  only be installed in the first partition anyway (hardcoded in the
  DTS). To ensure we are set to boot from the first partition, issue the
  following commands:

  > setsys bootpartition 0
  > savesys

* Download the image onto the device and boot from it:

  > tftpboot 0x81f00000 192.168.1.10:openwrt-realtek-rtl838x-zyxel_gs1900-24-v1-initramfs-kernel.bin
  > bootm

* Once OpenWrt has booted, scp the sysupgrade image to /tmp and flash it:

  > sysupgrade /tmp/openwrt-realtek-rtl838x-zyxel_gs1900-24-v1-squashfs-sysupgrade.bin

Signed-off-by: Martin Kennedy <hurricos@gmail.com>
2022-03-13 19:24:13 +01:00
INAGAKI Hiroshi
7b19770525 realtek: add support for I-O DATA BSH-G24MB
I-O DATA BSH-G24MB is a 24 port gigabit switch, based on RTL8382M.

Specification:

- SoC		: Realtek RTL8382M
- RAM		: DDR2 128 MiB (Nanya NT5TU128M8HE-AC)
- Flash		: SPI-NOR 16 MiB (Macronix MX25L12835FM2I-10G)
- Ethernet	: 10/100/1000 Mbps x24
  - port 1-8	: RTL8218B
  - port 9-16	: RTL8218B (SoC)
  - port 17-24	: RTL8218B
- LEDs/Keys	: 2x, 1x
- UART		: pin header on PCB
  - JP2: 3.3V, TX, RX, GND from rear side
  - 115200n8
- Power		: 100 VAC, 50/60 Hz
  - Plug	: IEC 60320-C13

Flash instruction using sysupgrade image:

1. Boot BSH-G24MB normally
2. Connect BSH-G24MB to the DHCP enabled network
3. Find the device's IP address and open the WebUI and login
   Note: by default, the device obtains IP address from DHCP server of
         the network
4. Open firmware update page ("ファームウェア アップデート")
5. Rename the OpenWrt sysupgrade image to "bsh-g24mb_v100.image" and
   select it
6. Press apply ("適用") button to perform update
7. Wait ~150 seconds to complete flashing

Note:

- BSH-G24MB has a power-related LED ("電源"), but it's not connected to
  the GPIO of the SoC or RTL8231 and cannot be controlled. Instead of
  it, use system status LED on other than running-state.

- "sys_loop" LED indicates system status and loop-detection status in
  stock firmware.

- BSH-G24MB has 2x os-image partitions named as "RUNTIME"/"RUNTIME2" in
  16 MiB SPI-NOR flash and the size of image per partition is only
  6848 KiB. The secondary image is never used on stock firmware, so also
  use it on OpenWrt to get more space.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2022-03-07 21:44:53 +01:00
Bjørn Mork
0890fb2df4 realtek: net: dsa: configure better brport flags when ports leave the bridge
Ensures that the DSA driver sets exactly the same default flags as the
bridge when a port joins or leaves.  Without this we end up with a
confusing flag mismatch, where DSA and bridge ports use different sets
of flags.

This is critical as the "learning" mismatch will be harmful to the
network, causing all traffic to be flooded on all ports.

The original commit was buggy, trying to set the flags one-by-one in a
loop.  This was not supported by the API and the end result was that
all but the last flag were cleared.  This bug was implicitly fixed
upstream by commit e18f4c18ab5b ("net: switchdev: pass flags and mask
to both {PRE_,}BRIDGE_FLAGS attributes").

This is a minimum temporary stop measure fix for the critical lack of
"learning" only.  The major API change associated with a full v5.12+
backport is neither required nor wanted. A simpler fix, moving the
call to dsa_port_bridge_flags() out of the loop,  has therefore been
merged into this modified backport.

Fixes: afa3ab54c0 ("realtek: Backport bridge configuration for DSA")
Signed-off-by: Bjørn Mork <bjorn@mork.no>
Acked-by: Daniel Golle <daniel@makrotopia.org>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
[fix typos in commit message]
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
2022-03-06 22:01:04 +02:00
John Audia
0989b7ad3a kernel: bump 5.10 to 5.10.102
Removed upstreamed:
	bcm4908/patches-5.10/180-i2c-brcmstb-fix-support-for-DSL-and-CM-variants.patch[1]

All other patches automatically rebased.

1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.102&id=f333c1916fd6b55900029bf8f918cc00009e2111

Build system: x86_64
Build-tested: bcm2711/RPi4B, mt7622/RT3200
Run-tested: bcm2711/RPi4B, mt7622/RT3200

Signed-off-by: John Audia <graysky@archlinux.us>
2022-03-01 21:38:36 +01:00
Sander Vanheule
66d8db01cc realtek: remove debugging code from timer
Remove some (dead) debugging code from the Realtek timer to clean up the
sources of this driver.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-02-20 16:23:58 +00:00
Sander Vanheule
9db651f4a2 realtek: use DT provided address for timers
The I/O base address for the timers was hardcoded into the driver,
or derived from the HW IRQ number as an even more horrible hack. All
supported SoC families have these timers, but with hardcoded addresses
the code cannot be reused right now.

Request the timer's base address from the DT specification, and store it
in a private struct for future reference.

Matching the second interrupt specifier, the address range for the
second timer is added to the DT specification.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-02-20 16:23:58 +00:00
Sander Vanheule
71810eb068 realtek: clean up RTL930x timer DT node
The Realtek timer node for RTL930x doesn't have any child nodes, making
the use of '#address-cells' quite pointless. It is also not an interrupt
controller, meaning it makes no sense to define '#interrupt-cells'.

The I/O address for this node is also wrong, but this is hidden by the
fact that the driver associated with this node bypasses the usual DT
machinery and does it's own thing. Correct the address to have a sane
value, even though it isn't actually used.

Fixes: a75b9e3ecb ("realtek: Adding RTL930X sub-target")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-02-20 16:23:58 +00:00
Sander Vanheule
fa20f2bfc7 realtek: ZyXEL GS1900-48: fix system LED polarity
When driven by a GPIO pin, the system LED needs to be configured as
active high. Otherwise the LED switches off after booting and
initialisation.

Fixes: 47f5a0a3ee ("realtek: Add support for ZyXEL GS1900-48 Switch")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-02-20 16:23:55 +00:00
Sander Vanheule
66140820e1 realtek: ZyXEL GS1900-48: drop status from gpio1
The default value for a DT node's status property is already "okay", so
there's no need to specify it again. Drop the status property to clean
up the DTS.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-02-20 16:23:55 +00:00
Sander Vanheule
a39fbaf23a realtek: use higher priority for timer interrupts
The assigned output index for the event timers was quite low, lower even
than the ethernet interrupt. This means that high network load could
preempt timer interrupts, possibly leading to all sorts of strange
behaviour.

Increase the interrupt output index of the event timers to 5, which is
the highest priority output and corresponds to the (otherwise unused)
MIPS CPU timer interrupt.

Fixes: a75b9e3ecb ("realtek: Adding RTL930X sub-target")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-02-20 16:23:55 +00:00
Sander Vanheule
4b31717fb0 realtek: move RTL8231 definitions to board files
The RTL8231 is an external chip, and not part of the SoC. That means
it is more appropriate to define it in the board specific (base) files,
instead of the DT include for the SoC itself.

Moving the RTL8231 definition also ensures that boards with no GPIO
expander, or an alternative one, don't have a useless gpio1 node label
defined.

Tested on a Netgear GS110TPPv1.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-02-20 16:23:55 +00:00
Sander Vanheule
004d4d66c8 realtek: fix node addresses for RTL839x
The address in some node names doesn't match the actual offset specified
in the DT node. Update the names to fix this.

While fixing the node names, also drop the unused node labels.

Fixes: 0a7565e536 ("realtek: Update rtl839x.dtsi for realtek,rtl-intc, new gpio controller remove RTL8231 node")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-02-20 16:23:55 +00:00
Sander Vanheule
1ca081000a realtek: consolidate bootargs again
Bootargs for devices in the realtek target were previously consolidated
in commit af2cfbda2b ("realtek: Consolidate bootargs"), since all
devices currently use the same arguments.

Commit a75b9e3ecb ("realtek: Adding RTL930X sub-target") reverted this
without any argumentation, so let's undo that.

Commit 0b8dfe0851 ("realtek: Add RTL931X sub-target") introduced the
old bootargs also for RTL931x, without providing any actual device
support. Until that is done, let's assume vendors will have done what
they did before, and use a baud rate of 115200.

Fixes: a75b9e3ecb ("realtek: Adding RTL930X sub-target")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-02-20 16:23:55 +00:00
Birger Koblitz
4d8020072e realtek: fix locking bug in rtl838x_hw_receive()
A Locking bug in the packet receive path was introduced with PR
#4973. The following patch prevents the driver from locking
after a few minutes with an endless flow of

[ 1434.185085] rtl838x-eth 1b00a300.ethernet eth0: Ring contention: r: 0, last a28000f4, cur a28000f8
[ 1434.208971] rtl838x-eth 1b00a300.ethernet eth0: Ring contention: r: 0, last a28000f4, cur a28000fc
[ 1434.794800] rtl838x-eth 1b00a300.ethernet eth0: Ring contention: r: 0, last a28000f4, cur a28000fc
[ 1435.049187] rtl838x-eth 1b00a300.ethernet eth0: Ring contention: r: 0, last a28000f4, cur a28000fc

Signed-off-by: Bjørn Mork <bjorn@mork.no>
Signed-off-by: Birger Koblitz <mail@birger-koblitz.de>
2022-02-18 12:35:03 +00:00
Sander Vanheule
a93dfff10e realtek: add RTL8231 chip detection
When initialising the driver, check if the RTL8231 chip is actually
present at the specified address. If the READY_CODE value does not match
the expected value, return -ENXIO to fail probing.

This should help users to figure out which address an RTL8231 is
configured to use, if measuring pull-up/-down resistors is not an
option.

On an unsuccesful probe, the driver will log:
    [    0.795364] Probing RTL8231 GPIOs
    [    0.798978] rtl8231_init called, MDIO bus ID: 30
    [    0.804194] rtl8231-gpio rtl8231-gpio: no device found at bus address 30

When a device is found, only the first two lines will be logged:
    [    0.453698] Probing RTL8231 GPIOs
    [    0.457312] rtl8231_init called, MDIO bus ID: 31

Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
2022-02-17 19:11:42 +02:00
Sander Vanheule
44f7cfd760 realtek: always require SMI bus ID for RTL8231
The SMI bus ID for RTL8231 currently defaults to 0, and can be
overridden from the devicetree. However, there is no value check on the
DT-provided value, aside from masking which would only cause value
wrap-around.

Change the driver to always require the "indirect-access-bus-id"
property, as there is no real reason to use 0 as default, and perform a
sanity check on the value when probing. This allows the other parts of
the driver to be simplified a bit.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
2022-02-17 19:11:37 +02:00
Sander Vanheule
5da2e0cc20 realtek: use automatic GPIO numbering for RTL8231
Set the gpio_chip.base to -1 to use automatic GPIO line indexing.
Setting base to 0 or a positive number is deprecated and should not be
used.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
2022-02-17 19:11:33 +02:00
Sander Vanheule
851212a714 realtek: fix RTL8231 gpio count
The RTL8231's gpio_chip.ngpio was set to 36, which is the largest valid
GPIO index. Fix the allowed number of GPIOs by setting ngpio to 37, the
actual line count.

Reported-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
2022-02-17 19:11:17 +02:00
Daniel Golle
eef7f17652 realtek: rtl83xx-phy: abstract and document PHY features
Replace magic values with more self-descriptive code now that I start
to understand more about the design of the PHY (and MDIO controller).

Remove one line before reading RTL8214FC internal PHY id which turned
out to be a no-op and can hence safely be removed (confirmed by
INAGAKI Hiroshi[1])

[1]: df8e6be59a (r66890713)

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
2022-02-17 15:37:03 +00:00
Birger Koblitz
68c66b0fa3 realtek: fix locking issues
Fixe a coupld of locking issues found by applying lock
debugging to the code.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Daniel Golle
b53202a8c3 realtek: switch to use generic MDIO accessor functions
Instead of directly calling SoC-specific functions in order to access
(paged) MII registers or MMD registers, create infrastructure to allow
using the generic phy_*, phy_*_paged and phy_*_mmd functions.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
2022-02-17 15:21:47 +00:00
Daniel Golle
af93bf6129 realtek: implement Clause-45 MDIO write on rtl931x
* Add missing Clause-45 write support for rtl931x
 * Switch to use helper functions in all Clause-45 access functions to
   make the code more readable.
 * More meaningful/unified debugging output (dynamic kprintf)

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
2022-02-17 15:21:47 +00:00
Daniel Golle
854458f986 realtek: backport Clause-45 MDIO helper functions
Import commit ("c6af53f038aa3 net: mdio: add helpers to extract clause
45 regad and devad fields") from Linux 5.17 to allow making the MDIO
code in the ethernet driver more readable.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
2022-02-17 15:21:47 +00:00
Birger Koblitz
0538dc693b realtek: add support for port led configuration on RTL93XX
Using the led-set attribute of a port in the dts we allow configuration
of the port leds. Each led-set is being defined in the led-set configuration
of the .dts, giving a specific configuration to steer the port LEDs via a serial
connection.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
caaac9ab3b realtek: Add support for the RTL8221B PHY
The RTL8221B PHY is a newer version of the RTL8226, also supporting
2.5GBit Ethernet. It is found with RTL931X devices such as the
EdgeCore ECS4125-10P

Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
08cf48c344 realtek: Add specific PHY polling options to support the Zyxel XGS1250/XGS1210
Both the Aquantia AQR113c and the RTL8226 PHYs in the Zyxel XGS1250 and the
Zyxel XGS1210 require special polling configuration settings in the
RTL930X_SMI_10GPHY_POLLING_REGxx_CFG configuration registers. Set them.
Additionally, for RTL 1GBit phys set the RTL930X_SMI_PRVTE_POLLING_CTRL bits
in the poll mask.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
3cab11ad13 realtek: Fix link status detection on RTL9302 for SFP modules
For SFP slots on the RTL9302, the link status is not correctly detected.
Use the link media status instead.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
0b8dfe0851 realtek: Add RTL931X sub-target
We add the RTL931X sub-target with kernel configuration for
a dual core MIPS InterAptive CPU.

Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
9ed6097054 realtek: Add HW support for RTL931X for PIE, L2 and STP aging
We add HW support routines for the RTL931X SoC family for handling
the Packet Inspection Engine, L2 table handling and STP aging.

Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
724e4af530 realtek: Store and Restore MC memberships for port enable/disable
We need to store and restore MC memberships in HW when a port joins or
leaves a bridge as well as when it is enabled or disabled, as these
properties should not change in these situations.

Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
d22923be66 realtek: Copy all BPDUs to the kernel
In order to receive STP information at the kernel level, we make sure
that all Bridge Protocol Data Units are copied to the CPU-Port.

Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
9d396fc1e8 realtek: Add L2 aging configuration functions for all SoC families
Instead of a generic L2 aging configuration function with complex
logic, we implement an individual function for all SoC types.

Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
f3c5e7ddcc realted: Add DSA bridge offload configuration
Add functionality to enable or disable L2 learning offload and port flooding
for RTL83XX.

Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
afa3ab54c0 realtek: Backport bridge configuration for DSA
Adds the DSA API for bridge configuration (flooding, L2 learning,
and aging) offload as found in Linux 5.12 so that we can implement
it in our drivver.

Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
32e5b5ee6b realtek: Add Link Aggregation (aka trunking) support
This adds LAG support for all 4 SoC families, including support
ofr the use of different distribution algorithm for the load-
balancing between individual links.

Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
8557b458e2 realtek: Backport LAG functionality for DSA
Add the LAG configuration API for DSA as found in Linux 5.12 so that we
can implement it in the dsa driver.

Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
77f3e2ea17 realtek: Cleanup setting inner/outer PVID and Ingress/Egres VLAN filtering
Use setting functions instead of register numbers in order to clean up the code.
Also use enums to define inner/outer VLAN types and the filter type.

Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
5b8b382df9 realtek: Add support for ZxXEL XGS1250-12 Switch
The ZyXEL XGS1250-12 Switch is a 11 + 1 port multi-GBit switch with
8 x 1000BaseT, 3 x 1000/2500/5000/10000BaseT Ethernet ports and
1 SFP+ module slot.

Hardware:
 - RTL9302B SoC
 - Macronix MX25L12833F (16MB flash)
 - Nanja NT5CC64M16GP-1 (128MB DDR3 SDRAM)
 - RTL8231 GPIO extender to control the port LEDs
 - RTL8218D 8x Gigabit PHY
 - Aquantia AQR113c 1/2.5/5/10 Gigabit PHYs
 - SFP+ 10GBit slot

Power is supplied via a 12V 2A standard barrel connector. At the
right side behind the grid is UART serial connector. A Serial
header can be connected to from the outside of the switch trough
the airvents with a standard 2.54mm header.
Pins are from top to bottom Vcc(3.3V), TX, RX and GND. Serial
connection is via 115200 baud, 8N1.

A reset button is accessble through a hole in the front panel

At the time of this commit, all ethernet ports work under OpenWRT,
including the various NBaseT modes, however the 10GBit SFP+ slot is not
supported.

Installation
--------------
* Connect serial as per the layout above. Connection parameters: 115200 8N1.
* Navigate to 'Management' in the OEM web interface and click on 'Firmware upgrade'
  to the left.
* Upload the OpenWrt initramfs image, and wait till the switch reboots.
* Connect to the device through serial and change the U-boot boot command.
  > fw_setenv bootcmd 'rtk network on; boota'
* Reboot, scp the sysupgrade image to /tmp, verify the checksum and flash it:
  > sysupgrade /tmp/openwrt-realtek-rtl930x-zyxel_xgs1250-12-squashfs-sysupgrade.bin
* Upon reboot, you have a functional OpenWrt installation. Leave the bootcmd
  value as is - without 'rtk network on' the switch will fail to initialise
  the network.

Web recovery
------------
The XGS1250-12 has a handy web recovery that will load when U-boot does
not find a bootable kernel. In case you would like to trigger the web
recovery manually, partially overwrite the firmware partition with some
zeroes:

  # dd if=/dev/zero of=/dev/mtd5 bs=1M count=2

If you have serial connected you'll see U-boot will start the web recovery
and print it's listening on 192.168.1.1, but by default it seems to be on
the OEM default IP for the switch - 192.168.1.3. The web recovery only
listens on HTTP (80) and *not* on 443 (HTTPS) unlike the web UI.

Return to stock
---------------
You can flash the ZyXEL firmware images to return to stock:

  # sysupgrade -F -n XGS1250-12_Firmware_V1.00(ABWE.1)C0.bix

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00