The sender domain has a DMARC Reject/Quarantine policy which disallows
sending mailing list messages using the original "From" header.
To mitigate this problem, the original message has been wrapped
automatically by the mailing list software.
Some devices like ZBT WE1326 and ZBT WF3526-P and some Netgear models need
to delay phy port initialization after calling the mt7621_pcie_init_port()
driver function to get into reliable boots for both warm and hard resets.
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
This commit fixes the following commit
f584fb2f7e kernel: import accepted MediaTek Ethernet patches
Unrefreshed patches caused the CI to fail.
Signed-off-by: Paul Spooren <mail@aparcar.org>
With 5.15 kernel version Linksys EAX500 family devices suffered from a
big regression where the Ethernet switch became silent and started to
malfunction.
It was discovered later that the cause was not really the kernel upgrade
itself but a hackish implementation of the hw implementation of these
special routers.
In the original Linksys source code, GPIO 63 was handled in a special way
and was reset on reboot.
Normally GPIO 63 is used for pcie2 reset but in every device we support,
pcie2 is actually never used as nothing is attached to it.
Linksys rerouted GPIO 63 to the switch reset pin and deviates from
common hw implementation.
Till now it was used an hack to handle this case... It was set pcie3 as
working (while actually nothing was connected), set it to output low
(for assert-deassert from the pcie init code) and be done with it.
The result was that the GPIO was reset for enough time in early boot and
everything worked correctly.
This hack implementation was born to fail from the very start and in
kernel 5.15 finally problem arised.
In 5.15 pcie code changed and now the GPIO reset pin is not asserted as
probe won't fail if nothing is connected to the line (the old behaviour)
This result in the switch hold the reset pin and the Ethernet switch
dead.
On top of that with 5.15 code got optimized and simply attaching the
GPIO reset to the mdio wasn't enough as the switch require at least 10ms
to be correctly reset.
So implement finally a correct solution where:
- pcie2 is correctly disabled (nothing attached, unused)
- drop the wrong output-low for pcie2 reset pin
- define GPIO 63 as switch reset
- Add the reset-gpios to the mdio0 node
- Set the reset-post-delay-us to 12ms to correctly give time the switch
to reset
Fixes: #10983
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
I tested kernel 5.15 on my device for several times without any problems.
In my tests, 5.15 kernel has performance improvements such MGLRU.
Finally, initial kernel 6.1 support is imminent. All ramips subtargets have
5.15 as testing kernel. So, it's time to change.
Tested on my Archer C6 v3.2 (mt7621)
Signed-off-by: Rodrigo B. de Sousa Martins <rodrigo.sousa.577@gmail.com>
[reformat commit subject and message]
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
Wrong pcie port number for WLAN causes missing 5g WLAN interface with 5.15
kernel. This changes port from pcie0 to pcie1 in dtsi.
[1.166330] mt7621-pci 1e140000.pcie: pcie0 no card, disable it (RST & CLK)
[1.180073] mt7621-pci 1e140000.pcie: pcie2 no card, disable it (RST & CLK)
[1.193889] mt7621-pci 1e140000.pcie: PCIE1 enabled
Signed-off-by: Mikhail Zhilkin <csharper2005@gmail.com>
We currently have build options to customize the IP address used in the
preinit phase of the boot process, but not to set the default LAN IP.
Introduce a boolean build option that, when enabled, results in the IP
address configured for the preinit phase, to be also used as the default
LAN IP address.
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
ipq807x does not compile-in hwmon core, and this is leading to the hwmon
code in AQR driver not being compiled due to IS_REACHABLE(CONFIG_HWMON)
evaluating to false as hwmon is being built as a module.
So, lets not compile-in Aquantia PHY driver so it can be included as kmod
instead to have functioning hwmon.
This allows using the thermal sensors in AQR-s as thermal zones for
cooling devices like fans.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Package the Aquantia AQR PHY driver as kmod.
This enables using the Aquantia driver with hwmon support on targets where
hwmon is not compiled-in.
Currently, in case when AQR driver is compiled-in but hwmon core is not
hwmon code in AQR driver will not get compiled because of macro
IS_REACHABLE(CONFIG_HWMON) evaluating to false.
Signed-off-by: Robert Marko <robimarko@gmail.com>
Replace a standalone init.d script with a platform implementation as
supported by netifd. This avoids a race between netifd and target
specific setups.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Package kmod-ipt-raw enables CONFIG_IP_NF_RAW and packages
iptable_raw.ko
According to kernel's net/netfilter/Kconfig there are only 3 kernel
symbols that depend on the IP_NF_RAW:
1. NETFILTER_XT_TARGET_CT (xt_CT.ko)
2. NETFILTER_XT_TARGET_NOTRACK (unused symbol?!)
3. NETFILTER_XT_TARGET_TRACE (xt_TRACE.ko)
Now: iptables-mod-conntrack-extra selects kmod-ipt-conntrack-extra which
provides: xt_helper.ko nf_conncount.ko xt_connlimit.ko xt_connmark.ko
xt_recent.ko and xt_connbytes.ko (none of them seems to require
iptable_raw.ko).
It seems there is no explicit reason for iptables-mod-conntrack-extra to
require kmod-ipt-raw (iptables_raw.ko).
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Replace a standalone init.d script with a platform implementation as
supported by netifd. This avoids a race between netifd and target
specific setups.
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Import some accepted and pending upstream patches for mtk_eth_soc,
replacing some semantically equivalent local patches and fixing issues
when operating the PCS in 1G SGMII mode.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Starting from Linux Kernel version 6.3 UBI devices will no longer be
considered virtual, but rather have an MTD device parent. Hence they
will no longer be listed under /sys/devices/virtual/ubi which is
used in multiple places in OpenWrt. Prepare for future kernels by
using /sys/class/ubi instead of /sys/devuces/virtual/ubi.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Merge network configurations in 02_network of Dynalink DL-WRX36 and
Xiaomi AX9000.
Reviewed-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Enable regulator-fixed to define the regulator of USB vbus on Buffalo
WXR-5950AX12.
Reviewed-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
APRESIA ApresiaLightGS120GT-SS (APLGS120GTSS) is a 16 + 4 ports gigabit
switch, based on RTL8382M.
Specifications:
- SoC : Realtek RTL8382M
- RAM : DDR3 256 MiB (Nanya NT5CC256M8JQ-EK)
- Flash : SPI-NOR 32 MiB (Macronix MX25L25635FMI-10G)
- Ethernet : 10/100/1000 Mbps x16 + 4
- port 1-8 : RTL8218B
- port 9-16 : RTL8382M, TP (SoC, RTL8218B)
- port 17-20 : RTL8214FC, TP/SFP (Combo)
- LEDs/Keys : 3x/1x
- UART : through-hole on PCB
- J6: 3.3V, TX, RX, GND from tri-angle marking side
- 115200n8
- Power : 100-120/200-240 VAC, 50/60 Hz
Max. 16 W, Avg 14 W (100 VAC)
- Plug : IEC 60320-C13
Flash instruction using factory image:
1. Boot ApresiaLightGS120GT-SS normally
2. Login to WebUI and open firmware page ("ファームウェア")
3. If the device is booted from image1, set active image for next
booting ("起動イメージ選択") to image2("イメージ2"), press apply
("適用") button and reboot the device to make booting from image2
4. On the WebUI, set active image to image1
5. Select the OpenWrt factory image and press update button ("更新")
6. Open reboot page ("再起動") and press reboot button ("再起動実行")
Notes:
- "ApresiaLightGS120GT-SS" is a model name and "APLGS120GTSS" is a model
number
- this device has 3x GPIO-controlled LEDs on PCB, but 1x LED
("green:unused") has no hole on the case
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
The cameo-related recipes can also be used for APRESIA ApresiaLightGS
series devices. So create common definition for the devices manufactured
by Cameo.
And also, the model name of ApresiaLightGS120GT-SS is too long for cameo
header (max: 20 bytes), so use additional variable "CAMEO_BOARD_MODEL"
in Build/cameo-headers instead of DEVICE_MODEL to use the custom name.
(default of CAMEO_BOARD_MODEL: DEVICE_MODEL)
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
This patch renames some Cameo specific definitions for image generation.
The same format is also used on APRESIA ApresiaLightGS series devices, not
D-Link specific.
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
The net_event_work struct is allocated, but only freed in a single case.
Move the allocation to the branch where it is actually needed, and free
it after the work has been done.
Fixes: 03e1d93e07 ("realtek: add driver support for routing offload")
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
The standard defines the A-MSDU header length field differently for mesh
compared to other modes. Deal with this accordingly and work around broken
implementations (e.g. ath10k, ath11k).
Signed-off-by: Felix Fietkau <nbd@nbd.name>
This updates to glibc to version 2.37.
Signed-off-by: Linhui Liu <liulinhui36@gmail.com>
[Update to current git commit]
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Specifications:
- Device: ASUS RT-AX54 (AX1800S/HP,AX54HP)
- SoC: MT7621AT
- Flash: 128MB
- RAM: 256MB
- Switch: 1 WAN, 4 LAN (10/100/1000 Mbps)
- WiFi: MT7905 2x2 2.4G + MT7975 2x2 5G
- LEDs: 1x POWER (blue, configurable)
1x LAN (blue, configurable)
1x WAN (blue, configurable)
1x 2.4G (blue, not configurable)
1x 5G (blue, not configurable)
Flash by U-Boot TFTP method:
- Configure your PC with IP 192.168.1.2
- Set up TFTP server and put the factory.bin image on your PC
- Connect serial port(rate:115200) and turn on AP, then interrupt "U-Boot Boot Menu" by hitting any key
Select "2. Upgrade firmware"
Press enter when show "Run firmware after upgrading? (Y/n):"
Select 0 for TFTP method
Input U-Boot's IP address: 192.168.1.1
Input TFTP server's IP address: 192.168.1.2
Input IP netmask: 255.255.255.0
Input file name: openwrt-ramips-mt7621-asus_rt-ax1800hp-squashfs-factory.bin
- Restart AP aftre see the log "Firmware upgrade completed!"
Signed-off-by: Karl Chan <exkc@exkc.moe>
All boards using this DTSI are expected to have
the same 16 MB MX25L12845EMI-10G flash chip,
or a larger one which can also use 40 MHz frequency.
Signed-off-by: Michael Pratt <mcpratt@pm.me>
Although VLANs are used, the "eth0" device by itself
does not have a valid MAC, so fix that with preinit script.
More initvals added by editing the driver to print switch registers,
after the bootloader sets them but before openwrt changes them.
The register bits needed for the QCA8337 switch
can be read from interrupted boot (tftpboot, bootm)
by adding print lines in the switch driver ar8327.c
before 'qca,ar8327-initvals' is parsed from DTS and written
for example:
pr_info("0x04 %08x\n", ar8xxx_read(priv, AR8327_REG_PAD0_MODE));
Signed-off-by: Michael Pratt <mcpratt@pm.me>
Use nvmem kernel subsystem to pull radio calibration data
with the devicetree instead of userspace scripts.
Existing blocks for caldata_extract are reordered alphabetically.
MAC address is set using the hotplug script.
Signed-off-by: Michael Pratt <mcpratt@pm.me>
FCC ID: A8J-ESR900
Engenius ESR1200 is an indoor wireless router with
a gigabit ethernet switch, dual-band wireless,
internal antenna plates, and a USB 2.0 port
**Specification:**
- QCA9557 SOC 2.4 GHz, 2x2
- QCA9882 WLAN PCIe mini card, 5 GHz, 2x2
- QCA8337N SW 4 ports LAN, 1 port WAN
- 40 MHz clock
- 16 MB FLASH MX25L12845EMI-10G
- 2x 64 MB RAM
- UART at J1 populated, RX grounded
- 6 internal antenna plates (omni-directional)
- 5 LEDs, 1 button (power, 2G, 5G, WAN, WPS) (reset)
**MAC addresses:**
Base MAC address labeled as "MAC ADDRESS"
MAC "wanaddr" is not similar to "ethaddr"
eth0 *:c8 MAC u-boot-env ethaddr
phy0 *:c8 MAC u-boot-env ethaddr
phy1 *:c9 --- u-boot-env ethaddr +1
WAN *:66:44 u-boot-env wanaddr
**Serial Access:**
RX on the board for UART is shorted to ground by resistor R176
therefore it must be removed to use the console
but it is not necessary to remove to view boot log
optionally, R175 can be replaced with a solder bridge short
the resistors R175 and R176 are next to the UART RX pin
**Installation:**
Method 1: Firmware upgrade page
OEM webpage at 192.168.0.1
username and password "admin"
Navigate to Settings (gear icon) --> Tools --> Firmware
select the factory.bin image
confirm and wait 3 minutes
Method 2: TFTP recovery
Follow TFTP instructions using initramfs.bin
use sysupgrade.bin to flash using openwrt web interface
**Return to OEM:**
MTD partitions should be backed up before flashing
using TFTP to boot openwrt without overwriting flash
Alternatively, it is possible to edit OEM firmware images
to flash MTD partitions in openwrt to restore OEM firmware
by removing the OEM header and writing the rest to "firmware"
**TFTP recovery:**
Requires serial console, reset button does nothing at boot
rename initramfs.bin to 'uImageESR1200'
make available on TFTP server at 192.168.99.8
power board, interrupt boot by pressing '4' rapidly
execute tftpboot and bootm
**Note on ETH switch registers**
Registers must be written to the ethernet switch
in order to set up the switch's MAC interface.
U-boot can write the registers on it's own
which is needed, for example, in a TFTP transfer.
The register bits from OEM for the QCA8337 switch
can be read from interrupted boot (tftpboot, bootm)
by adding print lines in the switch driver ar8327.c
before 'qca,ar8327-initvals' is parsed from DTS and written.
for example:
pr_info("0x04 %08x\n", ar8xxx_read(priv, AR8327_REG_PAD0_MODE));
Signed-off-by: Michael Pratt <mcpratt@pm.me>
FCC ID: A8J-ESR1750
Engenius ESR1750 is an indoor wireless router with
a gigabit ethernet switch, dual-band wireless,
internal antenna plates, and a USB 2.0 port
**Specification:**
- QCA9558 SOC 2.4 GHz, 3x3
- QCA9880 WLAN PCIe mini card, 5 GHz, 3x3
- QCA8337N SW 4 ports LAN, 1 port WAN
- 40 MHz clock
- 16 MB FLASH MX25L12845EMI-10G
- 2x 64 MB RAM
- UART at J1 populated, RX grounded
- 6 internal antenna plates (omni-directional)
- 5 LEDs, 1 button (power, 2G, 5G, WAN, WPS) (reset)
**MAC addresses:**
Base MAC address labeled as "MAC ADDRESS"
MAC "wanaddr" is similar to "ethaddr"
eth0 *:58 MAC u-boot-env ethaddr
phy0 *:58 MAC u-boot-env ethaddr
phy1 *:59 --- u-boot-env ethaddr +1
WAN *:10:58 u-boot-env wanaddr
**Serial Access:**
RX on the board for UART is shorted to ground by resistor R176
therefore it must be removed to use the console
but it is not necessary to remove to view boot log
optionally, R175 can be replaced with a solder bridge short
the resistors R175 and R176 are next to the UART RX pin
**Installation:**
Method 1: Firmware upgrade page
NOTE: ESR1750 might require the factory.bin
for ESR1200 instead, OEM provides 1 image for both.
OEM webpage at 192.168.0.1
username and password "admin"
Navigate to Settings (gear icon) --> Tools --> Firmware
select the factory.bin image
confirm and wait 3 minutes
Method 2: TFTP recovery
Follow TFTP instructions using initramfs.bin
use sysupgrade.bin to flash using openwrt web interface
**Return to OEM:**
MTD partitions should be backed up before flashing
using TFTP to boot openwrt without overwriting flash
Alternatively, it is possible to edit OEM firmware images
to flash MTD partitions in openwrt to restore OEM firmware
by removing the OEM header and writing the rest to "firmware"
**TFTP recovery:**
Requires serial console, reset button does nothing at boot
rename initramfs.bin to 'uImageESR1200'
make available on TFTP server at 192.168.99.8
power board, interrupt boot by pressing '4' rapidly
execute tftpboot and bootm
**Note on ETH switch registers**
Registers must be written to the ethernet switch
in order to set up the switch's MAC interface.
U-boot can write the registers on it's own
which is needed, for example, in a TFTP transfer.
The register bits from OEM for the QCA8337 switch
can be read from interrupted boot (tftpboot, bootm)
by adding print lines in the switch driver ar8327.c
before 'qca,ar8327-initvals' is parsed from DTS and written.
for example:
pr_info("0x04 %08x\n", ar8xxx_read(priv, AR8327_REG_PAD0_MODE));
Signed-off-by: Michael Pratt <mcpratt@pm.me>
FCC ID: A8J-ESR900
Engenius ESR900 is an indoor wireless router with
a gigabit ethernet switch, dual-band wireless,
internal antenna plates, and a USB 2.0 port
**Specification:**
- QCA9558 SOC 2.4 GHz, 3x3
- AR9580 WLAN PCIe on board, 5 GHz, 3x3
- AR8327N SW 4 ports LAN, 1 port WAN
- 40 MHz clock
- 16 MB FLASH MX25L12845EMI-10G
- 2x 64 MB RAM
- UART at J1 populated, RX grounded
- 6 internal antenna plates (omni-directional)
- 5 LEDs, 1 button (power, 2G, 5G, WAN, WPS) (reset)
**MAC addresses:**
Base MAC address labeled as "MAC ADDRESS"
MAC "wanaddr" is not similar to "ethaddr"
eth0 *:06 MAC u-boot-env ethaddr
phy0 *:06 MAC u-boot-env ethaddr
phy1 *:07 --- u-boot-env ethaddr +1
WAN *:6E:81 u-boot-env wanaddr
**Serial Access:**
RX on the board for UART is shorted to ground by resistor R176
therefore it must be removed to use the console
but it is not necessary to remove to view boot log
optionally, R175 can be replaced with a solder bridge short
the resistors R175 and R176 are next to the UART RX pin
**Installation:**
Method 1: Firmware upgrade page
OEM webpage at 192.168.0.1
username and password "admin"
Navigate to Settings (gear icon) --> Tools --> Firmware
select the factory.bin image
confirm and wait 3 minutes
Method 2: TFTP recovery
Follow TFTP instructions using initramfs.bin
use sysupgrade.bin to flash using openwrt web interface
**Return to OEM:**
MTD partitions should be backed up before flashing
using TFTP to boot openwrt without overwriting flash
Alternatively, it is possible to edit OEM firmware images
to flash MTD partitions in openwrt to restore OEM firmware
by removing the OEM header and writing the rest to "firmware"
**TFTP recovery:**
Requires serial console, reset button does nothing at boot
rename initramfs.bin to 'uImageESR900'
make available on TFTP server at 192.168.99.8
power board, interrupt boot by pressing '4' rapidly
execute tftpboot and bootm
**Note on ETH switch registers**
Registers must be written to the ethernet switch
in order to set up the switch's MAC interface.
U-boot can write the registers on it's own
which is needed, for example, in a TFTP transfer.
The register bits from OEM for the AR8327 switch
can be read from interrupted boot (tftpboot, bootm)
by adding print lines in the switch driver ar8327.c
before 'qca,ar8327-initvals' is parsed from DTS and written.
for example:
pr_info("0x04 %08x\n", ar8xxx_read(priv, AR8327_REG_PAD0_MODE));
Signed-off-by: Michael Pratt <mcpratt@pm.me>
Split the DTS to be used with similar boards made by Senao,
dual-band routers with Atheros / Qualcomm ethernet switch.
Set initvals for the switch in each device's DTS.
Set some common calibration nvmem-cells in DTSI.
While at it, fix MTD partition node names.
Signed-off-by: Michael Pratt <mcpratt@pm.me>
Use --rpath-link option instead of --rpath. The former is used only at
link-time, while the latter is searched at run-time as well.
Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
62c1740676 changed the location of the script from $(TOOLCHAIN_DIR)/usr
to $(TOOLCHAIN_DIR), but the TOOLCHAIN_SYSROOT used in wrapper.sh was
still expecting to find the script under usr/bin.
Fixes: 62c1740676 toolchain: fix the sysroot mess by getting...
Signed-off-by: Eneas U de Queiroz <cotequeiroz@gmail.com>
This reverts commit 52167feff8.
Fakeroot 1.30.1 broke building on certain hosts (32-bit archs).
As of 2023-01-10, this was apparently fixed in source code,
however, the version is still 1.30.1 (patch release),
so the old binaries are removed from the repository and replaced,
but the source provided by the repository remains the same.
Furthermore, there are some complicated issues blocking
the "testing" release from being bumped to a 1.30.x version.
Considering all of this, it would likely be better for this package
to follow the "testing" release instead of the "unstable" release,
which is still 1.29-1, so revert to that.
Link: https://bugs.debian.org/1023286
Link: https://tracker.debian.org/news/1407613/accepted-fakeroot-1301-11-source-into-unstable/
Link: https://qa.debian.org/excuses.php?package=fakeroot
Link: https://bugs.debian.org/1027803
Signed-off-by: Michael Pratt <mcpratt@pm.me>
Removed upstreamed patch: 010-padlock.patch
Changes between 1.1.1s and 1.1.1t [7 Feb 2023]
*) Fixed X.400 address type confusion in X.509 GeneralName.
There is a type confusion vulnerability relating to X.400 address processing
inside an X.509 GeneralName. X.400 addresses were parsed as an ASN1_STRING
but subsequently interpreted by GENERAL_NAME_cmp as an ASN1_TYPE. This
vulnerability may allow an attacker who can provide a certificate chain and
CRL (neither of which need have a valid signature) to pass arbitrary
pointers to a memcmp call, creating a possible read primitive, subject to
some constraints. Refer to the advisory for more information. Thanks to
David Benjamin for discovering this issue. (CVE-2023-0286)
This issue has been fixed by changing the public header file definition of
GENERAL_NAME so that x400Address reflects the implementation. It was not
possible for any existing application to successfully use the existing
definition; however, if any application references the x400Address field
(e.g. in dead code), note that the type of this field has changed. There is
no ABI change.
[Hugo Landau]
*) Fixed Use-after-free following BIO_new_NDEF.
The public API function BIO_new_NDEF is a helper function used for
streaming ASN.1 data via a BIO. It is primarily used internally to OpenSSL
to support the SMIME, CMS and PKCS7 streaming capabilities, but may also
be called directly by end user applications.
The function receives a BIO from the caller, prepends a new BIO_f_asn1
filter BIO onto the front of it to form a BIO chain, and then returns
the new head of the BIO chain to the caller. Under certain conditions,
for example if a CMS recipient public key is invalid, the new filter BIO
is freed and the function returns a NULL result indicating a failure.
However, in this case, the BIO chain is not properly cleaned up and the
BIO passed by the caller still retains internal pointers to the previously
freed filter BIO. If the caller then goes on to call BIO_pop() on the BIO
then a use-after-free will occur. This will most likely result in a crash.
(CVE-2023-0215)
[Viktor Dukhovni, Matt Caswell]
*) Fixed Double free after calling PEM_read_bio_ex.
The function PEM_read_bio_ex() reads a PEM file from a BIO and parses and
decodes the "name" (e.g. "CERTIFICATE"), any header data and the payload
data. If the function succeeds then the "name_out", "header" and "data"
arguments are populated with pointers to buffers containing the relevant
decoded data. The caller is responsible for freeing those buffers. It is
possible to construct a PEM file that results in 0 bytes of payload data.
In this case PEM_read_bio_ex() will return a failure code but will populate
the header argument with a pointer to a buffer that has already been freed.
If the caller also frees this buffer then a double free will occur. This
will most likely lead to a crash.
The functions PEM_read_bio() and PEM_read() are simple wrappers around
PEM_read_bio_ex() and therefore these functions are also directly affected.
These functions are also called indirectly by a number of other OpenSSL
functions including PEM_X509_INFO_read_bio_ex() and
SSL_CTX_use_serverinfo_file() which are also vulnerable. Some OpenSSL
internal uses of these functions are not vulnerable because the caller does
not free the header argument if PEM_read_bio_ex() returns a failure code.
(CVE-2022-4450)
[Kurt Roeckx, Matt Caswell]
*) Fixed Timing Oracle in RSA Decryption.
A timing based side channel exists in the OpenSSL RSA Decryption
implementation which could be sufficient to recover a plaintext across
a network in a Bleichenbacher style attack. To achieve a successful
decryption an attacker would have to be able to send a very large number
of trial messages for decryption. The vulnerability affects all RSA padding
modes: PKCS#1 v1.5, RSA-OEAP and RSASVE.
(CVE-2022-4304)
[Dmitry Belyavsky, Hubert Kario]
Signed-off-by: John Audia <therealgraysky@proton.me>
By specifying the flag "denx,fit" for partition "kernel", the kernel
try to find rootfs in the same partition during boot. Reality is that
the placement of rootfs is precisely determined by the name of another
partition -"ubi".
It was also found that on some device (for example devices with NAND
chips), the "Denx search engine" manages to find roots at the end of
partition "kernel", but such partition doesn't exist and is empty
there.
Fix this by removing the "denx,fit" flag from partition "kernel". With
this change the original behavior of searchif rootfs in partition "ubi"
is restored.
Signed-off-by: Oleg S <remittor@gmail.com>
