before spi transfer. use spi_prepare_message to setup spi hardware. it
will setup MSB, spi mode and speed
remove sys_freq member and speed check code
Signed-off-by: Michael Lee <igvtee@gmail.com>
SVN-Revision: 47578
* check clock rate, SPI mode, and word sizes
* setup spi polarity
* enable spi1 hw if need
Signed-off-by: Michael Lee <igvtee@gmail.com>
SVN-Revision: 47577
* fill struct according to the member order
* add error clean up
* set min/max spi speed. so we don't need to check again
Signed-off-by: Michael Lee <igvtee@gmail.com>
SVN-Revision: 47576
use loops_per_jiffy, spi clock speed and write bytes to get the
spi loop count. if loop to 0 than spi operation timeout.
remove usleep. we only write 1 byte to spi device. use busy loop
would be better.
Signed-off-by: Michael Lee <igvtee@gmail.com>
SVN-Revision: 47575
It turned out that mtk_nand driver uses some sophisticated accounting and a
general nand code must be patched.
This patch adds required read and erase calls to a general nand code. I
used a code for re6500 released by Linksys as a reference.
All required operations (erase, write and read) are usable. However I found
that jffs2 filesystem can be created only on top of a ubi volume. I tried
to create jffs2 directly on mtd device but pages with clean markers are
became uncorrectable.
Signed-off-by: Kirill Berezin <fyiwdt@gmail.com>
SVN-Revision: 47565
add the SDK alsa driver. this has only been tested on mt7628/88 and wm8960.
mt7620 is only compile tested.
Signed-off-by: John Crispin <blogic@openwrt.org>
SVN-Revision: 47205
When talking to an atmel controller we need 9600 or 250000 baud.
as 250000 does not exist we use 2500000.
Signed-off-by: John Crispin <blogic@openwrt.org>
SVN-Revision: 47204
when sleep mode is disable use MIPS as clocksource and clockevent instead of systick.
because MIPS timer has higher resolution 5ns less than systick 20us and
larger counter bits 32 > 16.
clean interrupt by write compare register at isr.
fix typo cause sleep mode not enable.
Signed-off-by: Michael Lee <igvtee@gmail.com>
SVN-Revision: 47122
Due to datasheet of rt3883 SoC rgmii1 port handles pins 84-95 and rgmii2 port handles pins 72-83. When this function ports gets added to rt3883_pinmux_data there's wrong pinmux bits set (RT3883_GPIO_MODE_GE1 manages 84-95 pins and RT3883_GPIO_MODE_GE2 manages 72-83). So when enabling rgmii2 as GPIO driver confuses hardware and nothing work, neither rgmii nor gpio.
Also in '0030-pinctrl-ralink-add-pinctrl-driver.patch' typo in name of rgmii2 port.
Signed-off-by: Nick Leiten <nickleiten@gmail.com>
SVN-Revision: 47118
The pinctrl-rt2880 code doesn't support multiple functions with the same
name. This will result in a incorrect pinmux configuration.
Signed-off-by: Sven Eckelmann <sven@open-mesh.com>
SVN-Revision: 46963
The MT7621 uses a 2 bit wide configuration of the sdhci, spi, mdio, pcie,
wdt, uart2 and uart3 in the GPIO_MODE register. It was correctly done
for sdhci, spi, pcie and wdt, The same has to be done for uart3, uart2
and mdio.
Signed-off-by: Sven Eckelmann <sven@open-mesh.com>
SVN-Revision: 46645
The PINS conntrolled by the SPI bits in the GPIO_MODE register is always
7 and not 8 for nand mode.
Signed-off-by: Sven Eckelmann <sven@open-mesh.com>
SVN-Revision: 46644
The uart3 setting in GPIO_MODE register is before the uart2 setting. Also
don't mix uart2 and uart3 function/groups.
Signed-off-by: Sven Eckelmann <sven@open-mesh.com>
SVN-Revision: 46643
