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https://github.com/openwrt/openwrt.git
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ramips: add speed and mode settings to spi-mt7621
Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 46956
This commit is contained in:
John Crispin
parent
38c28154bd
commit
85d5b9984d
@ -25,7 +25,7 @@
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obj-$(CONFIG_SPI_OC_TINY) += spi-oc-tiny.o
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--- /dev/null
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+++ b/drivers/spi/spi-mt7621.c
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@@ -0,0 +1,314 @@
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@@ -0,0 +1,479 @@
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+/*
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+ * spi-mt7621.c -- MediaTek MT7621 SPI controller driver
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+ *
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@ -70,6 +70,7 @@
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+
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+#define MT7621_SPI_OPCODE 0x04
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+#define MT7621_SPI_DATA0 0x08
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+#define MT7621_SPI_DATA4 0x18
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+#define SPI_CTL_TX_RX_CNT_MASK 0xff
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+#define SPI_CTL_START BIT(8)
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+
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@ -78,6 +79,10 @@
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+#define MT7621_SPI_MOREBUF 0x2c
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+#define MT7621_SPI_SPACE 0x3c
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+
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+#define MT7621_CPHA BIT(5)
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+#define MT7621_CPOL BIT(4)
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+#define MT7621_LSB_FIRST BIT(3)
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+
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+#define RT2880_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH)
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+
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+struct mt7621_spi;
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@ -108,17 +113,77 @@
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+ iowrite32(val, rs->base + reg);
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+}
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+
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+static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex)
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+{
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+ u32 master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
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+
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+ master &= ~(0xfff << 16);
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+ master |= 1 << 16;
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+ master |= 7 << 29;
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+ master |= 1 << 2;
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+ if (duplex)
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+ master |= 1 << 10;
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+
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+ mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
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+}
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+
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+static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
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+{
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+ struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
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+ int cs = spi->chip_select;
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+ u32 polar = 0;
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+
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+ mt7621_spi_reset(rs, cs);
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+ if (enable)
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+ polar = BIT(cs);
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+ mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
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+}
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+
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+static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed)
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+{
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+ struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
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+ u32 rate;
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+ u32 reg;
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+
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+ dev_dbg(&spi->dev, "speed:%u\n", speed);
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+
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+ rate = DIV_ROUND_UP(rs->sys_freq, speed);
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+ dev_dbg(&spi->dev, "rate-1:%u\n", rate);
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+
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+ if (rate > 4097)
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+ return -EINVAL;
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+
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+ if (rate < 2)
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+ rate = 2;
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+
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+ reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
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+ reg &= ~(0xfff << 16);
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+ reg |= (rate - 2) << 16;
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+ rs->speed = speed;
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+
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+ reg &= ~MT7621_LSB_FIRST;
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+ if (spi->mode & SPI_LSB_FIRST)
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+ reg |= MT7621_LSB_FIRST;
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+
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+ reg &= ~(MT7621_CPHA | MT7621_CPOL);
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+ switch(spi->mode & (SPI_CPOL | SPI_CPHA)) {
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+ case SPI_MODE_0:
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+ break;
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+ case SPI_MODE_1:
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+ reg |= MT7621_CPHA;
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+ break;
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+ case SPI_MODE_2:
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+ reg |= MT7621_CPOL;
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+ break;
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+ case SPI_MODE_3:
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+ reg |= MT7621_CPOL | MT7621_CPHA;
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+ break;
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+ }
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+ mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
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+
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+ return 0;
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+}
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+
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+static inline int mt7621_spi_wait_till_ready(struct spi_device *spi)
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+{
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+ struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
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@ -138,11 +203,12 @@
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+ return -ETIMEDOUT;
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+}
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+
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+static int mt7621_spi_transfer_one_message(struct spi_master *master,
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+static int mt7621_spi_transfer_half_duplex(struct spi_master *master,
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+ struct spi_message *m)
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+{
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+ struct mt7621_spi *rs = spi_master_get_devdata(master);
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+ struct spi_device *spi = m->spi;
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+ unsigned int speed = spi->max_speed_hz;
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+ struct spi_transfer *t = NULL;
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+ int status = 0;
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+ int i, len = 0;
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@ -175,6 +241,10 @@
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+ goto msg_done;
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+ }
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+
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+ if (mt7621_spi_prepare(spi, speed)) {
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+ status = -EIO;
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+ goto msg_done;
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+ }
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+ data[0] = swab32(data[0]);
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+ if (len < 4)
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+ data[0] >>= (4 - len) * 8;
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@ -221,21 +291,116 @@
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+ return 0;
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+}
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+
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+static int mt7621_spi_setup(struct spi_device *spi)
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+static int mt7621_spi_transfer_full_duplex(struct spi_master *master,
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+ struct spi_message *m)
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+{
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+ struct mt7621_spi *rs = spi_master_get_devdata(master);
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+ struct spi_device *spi = m->spi;
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+ unsigned int speed = spi->max_speed_hz;
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+ struct spi_transfer *t = NULL;
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+ int status = 0;
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+ int i, len = 0;
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+ int rx_len = 0;
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+ u32 data[9] = { 0 };
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+ u32 val = 0;
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+
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+ mt7621_spi_wait_till_ready(spi);
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+
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+ list_for_each_entry(t, &m->transfers, transfer_list) {
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+ const u8 *buf = t->tx_buf;
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+
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+ if (t->rx_buf)
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+ rx_len += t->len;
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+
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+ if (!buf)
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+ continue;
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+
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+ if (WARN_ON(len + t->len > 16)) {
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+ status = -EIO;
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+ goto msg_done;
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+ }
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+
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+ for (i = 0; i < t->len; i++, len++)
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+ data[len / 4] |= buf[i] << (8 * (len & 3));
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+ }
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+
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+ if (WARN_ON(rx_len > 16)) {
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+ status = -EIO;
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+ goto msg_done;
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+ }
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+
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+ if (mt7621_spi_prepare(spi, speed)) {
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+ status = -EIO;
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+ goto msg_done;
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+ }
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+
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+ for (i = 0; i < len; i += 4)
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+ mt7621_spi_write(rs, MT7621_SPI_DATA0 + i, data[i / 4]);
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+
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+ val |= len * 8;
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+ val |= (rx_len * 8) << 12;
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+ mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
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+
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+ mt7621_spi_set_cs(spi, 1);
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+
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+ val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
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+ val |= SPI_CTL_START;
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+ mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
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+
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+ mt7621_spi_wait_till_ready(spi);
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+
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+ mt7621_spi_set_cs(spi, 0);
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+
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+ for (i = 0; i < rx_len; i += 4)
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+ data[i / 4] = mt7621_spi_read(rs, MT7621_SPI_DATA4 + i);
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+
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+ //m->actual_length = len + rx_len;
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+ m->actual_length = rx_len;
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+
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+ len = 0;
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+ list_for_each_entry(t, &m->transfers, transfer_list) {
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+ u8 *buf = t->rx_buf;
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+
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+ if (!buf)
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+ continue;
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+
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+ for (i = 0; i < t->len; i++, len++)
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+ buf[i] = data[len / 4] >> (8 * (len & 3));
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+ }
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+
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+msg_done:
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+ m->status = status;
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+ spi_finalize_current_message(master);
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+
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+ return 0;
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+}
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+
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+static void mt7621_spi_reset(struct mt7621_spi *rs)
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+static int mt7621_spi_transfer_one_message(struct spi_master *master,
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+ struct spi_message *m)
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+{
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+ u32 master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
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+ struct spi_device *spi = m->spi;
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+ int cs = spi->chip_select;
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+
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+ master &= ~(0xfff << 16);
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+ master |= 13 << 16;
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+ master |= 7 << 29;
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+ master |= 1 << 2;
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+ if (cs)
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+ return mt7621_spi_transfer_full_duplex(master, m);
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+ return mt7621_spi_transfer_half_duplex(master, m);
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+}
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+
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+ mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
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+static int mt7621_spi_setup(struct spi_device *spi)
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+{
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+ struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
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+
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+ if ((spi->max_speed_hz == 0) ||
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+ (spi->max_speed_hz > (rs->sys_freq / 2)))
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+ spi->max_speed_hz = (rs->sys_freq / 2);
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+
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+ if (spi->max_speed_hz < (rs->sys_freq / 4097)) {
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+ dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
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+ spi->max_speed_hz);
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+ return -EINVAL;
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+ }
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+
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+ return 0;
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+}
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+
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+static const struct of_device_id mt7621_spi_match[] = {
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@ -279,7 +444,7 @@
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+
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+ master = spi_alloc_master(&pdev->dev, sizeof(*rs));
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+ if (master == NULL) {
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+ dev_dbg(&pdev->dev, "master allocation failed\n");
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+ dev_info(&pdev->dev, "master allocation failed\n");
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+ return -ENOMEM;
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+ }
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+
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@ -299,12 +464,12 @@
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+ rs->master = master;
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+ rs->sys_freq = clk_get_rate(rs->clk);
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+ rs->ops = ops;
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+ dev_dbg(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
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+ dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
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+ spin_lock_irqsave(&rs->lock, flags);
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+
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+ device_reset(&pdev->dev);
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+
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+ mt7621_spi_reset(rs);
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+ mt7621_spi_reset(rs, 0);
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+
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+ return spi_register_master(master);
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+}
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