Commit Graph

6 Commits

Author SHA1 Message Date
Daniel González Cabanelas
85ef69b202 mvebu: add support for Buffalo LinkStation LS421DE
Buffalo LinkStation LS421DE is a dual bay NAS, based on Marvell Armada 370

Hardware:
   SoC:         Marvell Armada 88F6707-A1
   CPU:         Cortex-A9 1200 MHz, 1 core
   Flash:       SPI-NOR 1 MiB, NAND 512 MiB
   RAM:         DDR3 512 MiB
   Ethernet:    1x 10/100/1000 Mbps
   USB:         1x 2.0, 1x 3.0
   SATA:        2x 3.0 Gbps
   LEDs/Input : 5x / 2x (1x button, 1x slide-switch)
   RTC:         Ricoh RS5C372A, I2C, no battery

Flash instruction (UART+TFTP):
  1. Downgrade the OEM firmware to 1.34 version (BUFFALO_BOOTVER=0.13)
  2. Remove any hard drive from inside the bays.
  3. Boot the Openwrt initramfs image using the U-Boot serial console:
         tftpboot 0x1200000 buffalo_ls421de-initramfs-kernel.bin
         bootm 0x1200000
  4. Flash the sysupgrade image using the Openwrt console:
         sysupgrade -n buffalo_ls421de-squashfs-sysupgrade.bin
  5. Wait until it finish, the device will reboot with Openwrt installed
     on the NAND flash.

Note:
  - Device shuting down doesn't work, even if the power slide switch is
    used. We must first, via MDIO, set the unused LED2 at the ethernet
    phy0 to off state. Reboot works ok.

Signed-off-by: Daniel González Cabanelas <dgcbueu@gmail.com>
Reviewed-by: Tomasz Maciej Nowak <tomek_n@o2.pl>
2020-04-13 22:41:14 +02:00
Tomasz Maciej Nowak
2d61f8821c mvebu: cortexa9: correct cpu subtype
Armada 370  processors have only 16 double-precision registers. The
change introduced by 8dcc108760 ("toolchain: ARM: Fix toolchain
compilation for gcc 8.x") switched accidentally the toolchain for mvebu
cortexa9 subtarget to cpu type with 32 double-precision registers. This
stems from gcc defaults which assume "vfpv3-d32" if only "vfpv3" as mfpu
is specified. That change resulted in unusable image, in which kernel
will kill userspace as soon as it causing "Illegal instruction".

Ref: https://forum.openwrt.org/t/gcc-was-broken-on-mvebu-armada-370-device-after-commit-on-2019-03-25/43272
Fixes: 8dcc108760 ("toolchain: ARM: Fix toolchain compilation for
gcc 8.x")
Signed-off-by: Tomasz Maciej Nowak <tomek_n@o2.pl>
2020-03-28 22:58:36 +01:00
Adrian Schmutzler
1fa04b5d9f mvebu: split base-files across subtargets
For the mvebu target in particular, there is a lot of files in
base-files that are only relevant for one subtarget. Improve
overview and reduce size per subtarget by moving/splitting
base-files depending on the subtarget they belong to.

While at it, consolidate 01_leds by using the model part of
the board name as variable.

Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Acked-by: Tomasz Maciej Nowak <tomek_n@o2.pl>
2020-01-21 14:24:49 +01:00
Tomasz Maciej Nowak
9f6c4ba25c mvebu: move HARDEN_BRANCH_PREDICTOR to common config
This symbol is enabled in all subtargets, move it to common kernel
config.

Signed-off-by: Tomasz Maciej Nowak <tomek_n@o2.pl>
Acked-by: Rosen Penev <rosenp@gmail.com>
2019-01-27 00:16:14 +01:00
Koen Vandeputte
ca88f4153f kernel: bump 4.14 to 4.14.77
Refreshed all patches.

Altered patches:
- 666-Add-support-for-MAP-E-FMRs-mesh-mode.patch

New symbol for arm targets:
- HARDEN_BRANCH_PREDICTOR

Compile-tested on: ar71xx, cns3xxx, imx6
Runtime-tested on: ar71xx, cns3xxx, imx6

Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
2018-10-19 10:01:57 +02:00
Hauke Mehrtens
be3da900cd mvebu: Add subtarget for Cortex A9 build
This is in preparation for adding a subtarget for the Cortex A53 later.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2018-03-10 01:15:21 +01:00