The WLAN + WED reset sequence relies on being able to receive interrupts from
the card, in order to synchronize individual steps with the firmware.
When WED is stopped, leave interrupts running and rely on the driver turning
off unwanted ones.
WED DMA also needs to be disabled before resetting.
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Refresh patches for Linux 6.1 which no longer apply cleanly after
adding patches to fix ethernet rx hang issue on MT7981/MT7986.
Fixes: ede34465de ("mediatek: fix ethernet rx hang issue on MT7981/MT7986")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-+-------------------------+-
| Model | NIC |
-+-------------------------+-
| All | MT7603 + MT7615 |
-+-------------------------+-
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
Some MT7915 calibration data consists of two parts. The first part
"eeprom" size is 0xe00. The second part "precal" size is 0x19c10.
Though some devices may not have precal data, it's better to assume
that precal data exists as no users/developers confirm it. On the
other hand, some devices definitely do not contain precal data
because the EEPROM partition size is smaller than the precal NVMEM
cell size.
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
Innacomm W3400V6 is an xDSL B/G wireless router based on Broadcom
BCM6328 SoC.
SoC: Broadcom BCM6328
CPU: BMIPS4350 V8.0, 320 MHz, 1 core
Flash: SPI-NOR 8MB, MX25L6406E
RAM: 64 MB
Ethernet: 4x 10/100 Mbps
Switch: Integrated
Wireless: 802.11b/g, BCM4312
LEDs/Buttons: 9x / 2x
Flash instruction, web UI:
1. Set a static IP on your computer compatible with 192.168.1.1, i.e
192.168.1.100.
2. Connect the ethernet cable from your computer to the router.
3. Make sure the router is powered off.
4. Press the reset button, don't release it yet!
5. While pressing reset, power on the router.
6. Wait 10 seconds or more.
Note: The power LED is red at first then turns to solid green when
ready.
7. Release the reset button.
8. Browse to 192.168.1.1
9. Select .bin file.
10. Upgrade the image.
11. Wait for it to reboot.
Signed-off-by: Sieng-Piaw Liew <liew.s.piaw@gmail.com>
[Fix cfe nvmem-layout and pinctrl_leds indentation]
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
The original configuration might be copied from bcm2710 which uses
cortex A53 rather than A72 in BCM2711, without errata might be harmful
to system stability and security.
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Drop PSGMII PHY patch as it has been moved to generic in preparation for
the PHY driver to be also used for ipq807x SoC as the same PHY is also
used there.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Backport FIELD_PREP_CONST patch needed for at803x backport patches to
correctly compile and work.
This MACRO is needed to treat values derived from FIELD_PREP usage as
const to be used by switch case or other needed usage.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Part 1 of #13629 split.
* Sets the LAN 2 MAC address in the DTS by deriving it from LAN 1's
address. The factory OS derives this from the `eth1addr` u-boot env
variable, but the nvmem_u-boot-env driver doesn't support parsing MAC
addresses from fields other than `ethaddr`. But for all of the device
samples I've checked (~10) it derives the correct MAC.
* Updates 02_network to ensure that interfaces are assigned to roles
correctly and consistently.
Signed-off-by: Bryan Berg <bdb@north-eastham.org>
Initial backport of at803x PHY driver cleanup. This is in preparation
for split and addition of new PHY Family based on at803x needed for
ipq807x and other IPQ Series SoC.
Other affected patch are automatically refreshed with
make target/linux/refresh
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
The register constants were duplicated in net/dsa/rtl83xx/debugfs.c and asm
mach-rtl838x/mach-rtl83xx.h. This commit removes this duplication.
Signed-off-by: Peter Körner <git@mazdermind.de>
According to https://svanheule.net/realtek/maple/register/led_sw_ctrl and also
drivers/net/dsa/rtl83xx/debugfs.c LED_SW_CTRL on the RTL838X should be 0xa00c
not 0x0128. Please note, that is is 0x0128 on the RTL8390/cypress SOC family.
Signed-off-by: Peter Körner <git@mazdermind.de>
the given code-format did not correctly express the condition and made the code
harder to read then necessary.
Signed-off-by: Peter Körner <git@mazdermind.de>
Fine tuning PR: openwrt/openwrt#14355 Ref: 5a82bb909b
("mediatek: GL-MT6000: Add missing LED state definitions")
As the only LED is using white in the stock firmware when the device is
running and blue for the bootloader I suggest following changes:
- Using blue for the BL and preinit+failsafe
- White for normal operation (like the original FW) and sysupgrade
With this changes it's clear by looking to the LED in which operation
mode the device is and a possible BL stuck can be seen easily.
Tested with [GL-MT6000](https://openwrt.org/toh/gl.inet/gl-mt6000).
Signed-off-by: Thomas Schröder <tschroeder_github@outlook.com>
Tested-by: Hannu Nyman <hannu.nyman@iki.fi>
Enable LED driver LP5562 on HAZE device tree and include its kernel
module package on default package for HAZE.
Signed-off-by: CheWei Chien <chewei.chien@wnc.com.tw>
Some devices (MX42CF) have a wrong MAC address configuration. The correct one is located only on the devinfo partition.
Signed-off-by: Paweł Owoc <frut3k7@gmail.com>
This reduces the size of a single imagebuilder by about 40MB
In example for the target ath79 it would be the sum of generic and <target> directories, so about 16MB,
instead of the whole size of the target directory, about 53MB:
11M target/linux/generic/
3.9M target/linux/ath79/
Signed-off-by: a-gave <agave@dracaena.it>
The nvmem-cells is deprecated. Also simplify mac address settings.
Fixes: b4086f4 ("mediatek: add support for YunCore AX835")
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
The mac address of the network port under the switch is
the same as the corresponding gmac by default, so there
is no need to repeat the setting. Compile test only.
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
The GS110TUP v1 is a managed switch similar to the GS110TPP v1, but with
port 10 as SFP instead of RJ-45 and a total budget of 240 watts. Ports
1-4 support 60-watt 802.3bt PoE and ports 5-8 support 30-watt 802.3at.
The flash layout of the two switches are identical, and the U-Boot
configurations are the same except for having a different magic number,
so installation can be done via the same U-Boot method.
The following command will be needed to enable the port LEDs as per
https://forum.openwrt.org/t/72510/51 :
fw_setenv bootcmd "rtk network on; boota"
Additionally, port 9 (1000base-T from a separate QSGMII PHY) does not
function without this. Port 10 was not tested as no SFP module was
available.
Signed-off-by: Jacob Potter <jacob@j4cbo.com>
[rebase on merged flash layout]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Flash layouts for GS108Tv3, GS110TPPv1, GS308Tv1 and GS310TPv1 are
almost identical, except for the uimage header magic.
Move the flash layout to the common dtsi, and only place the magic value
in the device dts files.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Read back the reset register in order to flush the cache. This fixes
spurious reboot hangs on TP-Link TL-WDR3600 and TL-WDR4300 with Zentel
DRAM chips.
This issue was fixed in the past, but switching to the reset-driver
specific implementation removed the cache barrier which was previously
implicitly added by reading back the register in question.
Link: https://github.com/freifunk-gluon/gluon/issues/2904
Link: https://github.com/openwrt/openwrt/issues/13043
Link: https://dev.archive.openwrt.org/ticket/17839
Link: f8a7bfe1cb2c ("MIPS: ath79: fix system restart")
Signed-off-by: David Bauer <mail@david-bauer.net>
TP-Link RE365 is a wireless range extender, hardware-wise resembles
RE305 with slight changes regarding buttons and LEDs.
Specification
SoC: MediaTek MT7628AN
RAM: 64 MiB DDR2
Flash: 8 MiB SPI NOR
WiFi: 2.4 GHz 2T2R integrated
5 GHz 2T2R MediaTek MT7612EN conncted to PCIe lanes
Ethernet: 1x 10/100 Mbps integrated
LEDs: 6x GPIO controlled
Buttons: 4x GPIO controlled
UART: row of 4 holes marked on PCB as J1, starting count from white
triangle
1. VCC (3.3V), 2. GND, 3. RX, 4. TX
baud: 57600, parity: none, flow control: none
Installation
1. Open web management interface.
2. Go to Settings > System Tools > Firmware upgrade.
3. Select "Browse" and select the OpenWrt image with factory.bin suffix.
4. After selecting "Upgrade" firmware writing process will start.
5. Wait till device reboots, power LED should stay solid when it's fully
booted, then it's ready for configuration through LAN port.
Additional information
With how device manufacturer patrtitioned the flash memory, it's possible
that with default packages set, initial factory.bin image won't be
created. In such case, try to reduce packages amount or use older release
for initial conversion to OpenWrt. Later You can use sysupgrade.bin
image with full set of packages because OpenWrt uses unpartitioned flash
memory space unused by vendor firmware.
Reverting to vendor firmware involves converting firmware using
tplink-safeloader with -z option (can be found in ImageBuilder or SDK)
and forcibly applying converted firmware as sysupgrade.
Known issues
WARNING: after removing casing of the device one is exposed to high
voltage and is in a risk of being electrocuted.
Caution when interfacing whith bootloader, saving its environment either
by issuing "saveenv" or selecting option "1: Load system code to SDRAM
via TFTP." in boot menu, any of those will lead to overwriting part of
kernel. This will lead to need of firmware recovery. The cause of this
issue is bootloader having environment offset on flash at 0x40000,
while kernel starts from 0x20000.
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
[Wrap long line in DTS]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Before, PVID is reset for all ports and goes out of bounds. Also, PVID
is later changed by dsa configuration by `ip link` and `bridge vlan`
commands, this does not change the CPU port PVID and CPU PVID stays 0.
It does not allow sending packets from OpenWrt to any connected devices
unless default configuration is changed
This change iterates up to and including cpu_port and sets default PVID
to 1. For lan* ports PVID can be configured with `ip link` and `bridge
vlan` commands
Acked-by: Simon Wunderlich <sw@simonwunderlich.de>
Signed-off-by: Harshal Gohel <hg@simonwunderlich.de>
