Backport initial LEDs hw control support. Currently this is limited to
only rx/tx and link events for the netdev trigger but the API got
accepted and the additional modes are working on and will be backported
later.
Refresh every patch and add the additional config flag for QCA8K new
LEDs support.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Kernel 5.15.111 includes backport of commit
("firmware: qcom_scm: Clear download bit during reboot") which is causing
reboot on ipq40xx to stop working, more precisely the board will hang after
reboot is called with:
root@OpenWrt:/# reboot
root@OpenWrt:/# [ 76.473541] device lan1 left promiscuous mode
[ 76.474204] br-lan: port 1(lan1) entered disabled state
[ 76.527975] device lan2 left promiscuous mode
[ 76.530301] br-lan: port 2(lan2) entered disabled state
[ 76.579376] device lan3 left promiscuous mode
[ 76.581698] br-lan: port 3(lan3) entered disabled state
[ 76.638434] device lan4 left promiscuous mode
[ 76.638777] br-lan: port 4(lan4) entered disabled state
[ 76.978489] qca8k-ipq4019 c000000.switch wan: Link is Down
[ 76.978883] device eth0 left promiscuous mode
[ 76.987077] ipqess-edma c080000.ethernet eth0: Link is Down
[
Format: Log Type - Time(microsec) - Message - Optional Info
Log Type: B - Since Boot(Power On Reset), D - Delta, S - Statistic
S - QC_IMAGE_VERSION_STRING=BOOT.BF.3.1.1-00123
S - IMAGE_VARIANT_STRING=DAABANAZA
S - OEM_IMAGE_VERSION_STRING=CRM
S - Boot Config, 0x00000021
S - Reset status Config, 0x00000010
S - Core 0 Frequency, 0 MHz
B - 261 - PBL, Start
B - 1339 - bootable_media_detect_entry, Start
B - 1679 - bootable_media_detect_success, Start
B - 1693 - elf_loader_entry, Start
B - 5076 - auth_hash_seg_entry, Start
B - 7223 - auth_hash_seg_exit, Start
B - 578349 - elf_segs_hash_verify_entry, Start
B - 696356 - PBL, End
B - 696380 - SBL1, Start
B - 787236 - pm_device_init, Start
D - 7 - pm_device_init, Delta
B - 788701 - boot_flash_init, Start
D - 52782 - boot_flash_init, Delta
B - 845625 - boot_config_data_table_init, Start
D - 3836 - boot_config_data_table_init, Delta - (419 Bytes)
B - 852841 - clock_init, Start
D - 7566 - clock_init, Delta
B - 864883 - CDT version:2,Platform ID:9,Major ID:0,Minor ID:0,Subtype:64
B - 868413 - sbl1_ddr_set_params, Start
B - 873402 - cpr_init, Start
D - 2 - cpr_init, Delta
B - 877842 - Pre_DDR_clock_init, Start
D - 4 - Pre_DDR_clock_init, Delta
D - 13234 - sbl1_ddr_set_params, Delta
B - 891155 - pm_driver_init, Start
D - 2 - pm_driver_init, Delta
B - 909105 - Image Load, Start
B - 1030210 - Boot error ocuured!. Error code: 303d
So, until a proper fix is found, lets revert the culprit patch to have
reboot working again.
Fixes: 228e0e1039 ("kernel: bump 5.15 to 5.15.111")
Signed-off-by: Robert Marko <robimarko@gmail.com>
Add patch commenting unused sdhci function, hopin this will be dropped
when the problem is actually found.
Fix compilation warning:
drivers/mmc/host/sdhci-msm.c:1781:13: error: 'sdhci_msm_set_clock' defined but not used [-Werror=unused-function]
1781 | static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
| ^~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Upstream commit ("net: phylink: add generic validate implementation") was
backported, however PSGMII PHY mode patch for ipq40xx was not updated to
add PSGMII to phylink_get_linkmodes() so the following warning would be
printed during kernel compilation:
drivers/net/phy/phylink.c: In function 'phylink_get_linkmodes':
drivers/net/phy/phylink.c:360:9: error: enumeration value 'PHY_INTERFACE_MODE_PSGMII' not handled in switch [-Werror=switch]
360 | switch (interface) {
| ^~~~~~
Resolve the warning by adding the PSGMII mode to phylink_get_linkmodes().
Signed-off-by: Robert Marko <robimarko@gmail.com>
Similar to the lantiq platform, these are required for DSL support.
Signed-off-by: Martin Schiller <ms.3headeddevs@gmail.com>
[switch to kernel 5.10 and 5.15]
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
[update patches based on UGW 8.5.2.10, remove 5.10 support]
Signed-off-by: Andre Heider <a.heider@gmail.com>
Remove ess-psgmii@98000, edma@c080000 and ess-switch@c000000 nodes.
These nodes are not used after the DSA conversion, but were left over
in a few devices added recently.
ZTE MF289F is omitted on purpose, as for it, these nodes will be removed
together with DSA conversion.
Build tested only, as I only have MF286D from those devices.
Reviewed-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
Qualcomm IPQ40xx SoC-s have a variant of QCA8337N switch built-in.
It shares most of the stuff with its external counterpart, however it is
modified for the SoC.
Namely, it doesn't have second CPU port (Port 6), so it has 6 ports
instead of 7.
It also has no built-in PHY-s but rather requires external PSGMII based
companion PHY-s (QCA8072 and QCA8075) for which it first needs to carry
out calibration before using them.
PSGMII has a SoC built-in PHY that is used to connect to the PHY-s which
unfortunately requires some magic values as the datasheet doesnt document
the bits that are being set or the register at all.
Since its built-in it is MMIO like other peripherals and doesn't have its
own MDIO bus but depends on the SoC provided one.
CPU connection is at Port 0 and it uses some kind of a internal connection
and no traditional RGMII/SGMII.
It also doesn't use in-band tagging like other qca8k switches so a shinfo
based tagger is used.
This is based on the current OpenWrt qca8k version that has been imported
from generic target.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
PSGMII is a Qualcomm specific mode similar to QSGMII but it has 5 SGMII
lines instead of 4 in QSGMII.
This just adds the support for the PHY layer to be able to identify the
mode for further use.
It is required for the DSA driver.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
IPQESS is the EDMA replacement driver for the IPQ40xx SoC built-in
ethernet controller.
Unlike EDMA it is Phylink based and doesnt touch PHY-s directly.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
There is no point in using a DT property to trigger setting the PSGMII
PHY AZ transmitting ability.
Especially since EEE can be disabled using ethtool anyway.
Fixup the mask for setting the workaround as only BIT(0) is actually being
changed and use the phy_clear_bits_mmd helper instead of reading, then
clearing the bit and writing back as it does everything for us.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
IPQ40xx requires a special DSA tag driver despite using the QCA8337N
switch.
However they have changed the header format and the existing QCA tag
driver cannot be reused.
For details on how it actually works and else read the patch commit
description.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
In order to start working on IPQESS + DSA drop the old ESSEDMA + AR40xx
driver combo.
Remove the kernel symbols, disable swconfig and drop swconfig package
as they are not needed anymore.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Adjusting dts will cause a rebuild of whole kernel as the buildroot
considers this a part of kernel source. It's a royal PITA when trying to
prepare support for new device, since this takes a lot of time on slower
systems. As it stands, buildroot itself, with own rule, also compiles
dtbs and the results are $(KDIR)/image-$(DEVICE_DTS).dtb. With setting
DEVICE_DTS_DIR to directory holding the device dts (similarly to some
other targets), buildroot doesn't consider changed dts as part of kernel
source and rebuilds only dtb. This really speeds up development. And
since the kernel built dts are no longer used, drop the paches adding
dtses to its build.
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
Reviewed-by: Robert Marko <robimarko@gmail.com>
The MikroTik wAP ac (RBwAPG-5HacD2HnD) is a dual-band dual-radio
802.11ac wireless access point with integrated antenna and two Ethernet
ports in a weatherproof enclosure. See
https://mikrotik.com/product/wap_ac for more information.
Important: this is the new ipq40xx-based wAP ac, not the older
ath79-based wAP ac (RBwAPG-5HacT2HnD), already supported in OpenWrt.
Specifications:
- SoC: Qualcomm Atheros IPQ4018
- CPU: 4x ARM Cortex A7
- RAM: 128MB
- Storage: 16MB NOR flash
- Wireless
- 2.4GHz: Built-in IPQ4018 (SoC) 802.11b/g/n 2x2:2, 2.5 dBi antennae
- 5GHz: Built-in IPQ4018 (SoC) 802.11a/n/ac 2x2:2, 2.5 dBi antennae
- Ethernet: Built-in IPQ4018 (SoC, QCA8075), 2x 1000/100/10Mb/s ports,
one with 802.3af/at PoE in
Installation:
Boot the initramfs image via TFTP, then flash the sysupgrade image using
sysupgrade. Details at https://openwrt.org/toh/mikrotik/common.
Notes:
This preserves the MAC addresses of the physical Ethernet ports:
- eth0 corresponds to the physical port labeled ETH1 and has the base
MAC address. This port can be used to power the device.
- eth1 corresponds to the physical port labeled ETH2 and has a MAC
address one greater than the base.
MAC addresses are set from /lib/preinit/05_set_iface_mac_ipq40xx.sh
rather than /etc/board.d/02_network so that they are in effect for
preinit. This should likely be done for other MikroTik devices and
possibly other non-MikroTik devices as well.
As this device has 2 physical ports, they are each connected to their
respective PHYs, allowing the link status to be visible to software.
Since they are not marked on the case with any role (such as LAN or
WAN), both are bridged to the lan network by default, although this can
easily be changed if needed.
Signed-off-by: Mark Mentovai <mark@mentovai.com>
The Meraki MR74 is part of the "Insect" series. This device is
essentially an outdoor variant of the MR33 with identical hardware, but
requiring a config@3 DTS option to be set to allow booting with the
stock u-boot.
The install procedure is replicated from the MR33, with the exception
being that the MR74 sysupgrade image must be used.
Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
Linux' upstream MTD-Maintainer Miquèl Raynal noted:
|Reverting seems the safest option here, not knowing how many devices
|have these damaged/counterfeit chips. If it is just a couple and only on
|Fritzboxes, as suggested in the Github issue this patch could be
|carried through OpenWrt and that would seem more future proof IMHO.
This patch follows up with the first patch. It actually
moves the patches out of target/linux/generic/pending into
the ipq40xx's patch heap and adds a little note what happend.
For more information, discussions or reports about bad TC58NVG0S3Hs,
please visit the OpenWrt's Github Issue #9962:
<https://github.com/openwrt/openwrt/issues/9962>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
This patch adds support for Linksys WHW01 v1 ("Velop") [FCC ID Q87-03331].
Specification
-------------
SOC: Qualcomm IPQ4018
WiFi 1: Qualcomm QCA4019 IEEE 802.11b/g/n
WiFi 2: Qualcomm QCA4019 IEEE 802.11a/n/ac
Bluetooth: Qualcomm CSR8811 (A12U)
Ethernet: Qualcomm QCA8072 (2-port)
SPI Flash 1: Mactronix MX25L1605D (2MB)
SPI Flash 2: Winbond W25M02GV (256MB)
DRAM: Nanya NT5CC128M16IP-DI (256MB)
LED Controller: NXP PCA963x (I2C)
Buttons: Single reset button (GPIO).
Notes
-----
There does not appear to be a way to trigger TFTP recovery without entering
U-Boot. The device must be opened to access the serial console in order to
first flash OpenWrt onto a device from factory.
The device has automatic recovery backed by a second set of partitions on
the larger of the two SPI flash ICs. Both the primary and secondary must
be flashed to prevent accidental rollback to "factory" after 3 failed boot
attempts.
Serial console
--------------
A serial console is available on the following pins of the populated J2
connector on the device mainboard (115200 8n1).
(<-- Top of PCB / Device)
J2
[o o o o o o]
| | |
| | `-- GND
| `---- TX
`--------- RX
Installation instructions
-------------------------
1. Setup TFTP server with server IP set to 192.168.1.236.
2. Copy compiled `...squashfs-factory.bin` to `nodes-jr.img` in tftp root.
3. Connect to console using pinout detailed in the serial console section.
4. Power on device and press enter when prompted to drop into U-Boot.
5. Flash first partition device via `run flashimg`.
6. Once complete, reset device and allow to power up completely.
7. Once comfortable with device upgrade reboot and drop back into U-Boot.
8. Flash the second partition (recovery) via `run flashimg2`.
Revert to "factory"
-------------------
1. Download latest firmware update from vendor support site.
2. Copy extracted `.img` file to `nodes-jr.img` in tftp root.
3. Connect to console using pinout detailed in the serial console section.
4. Power on device and press enter when prompted to drop into U-Boot.
5. Flash first partition device via `run flashimg`.
6. Once complete, reset device and allow to power up completely.
7. Once comfortable with device upgrade reboot and drop back into U-Boot.
8. Flash the second partition (recovery) via `run flashimg2`.
Link: https://github.com/openwrt/openwrt/pull/3682
Signed-off-by: Peter Adkins <peter@sunkenlab.com>
(calibration from nvmem, updated to 5.10+5.15)
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Patch that corrects sleep clock frequency has already been backported
to 5.15 stable so remove the duplicate patch.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
