Qxwlan E750G v8 is based on Qualcomm QCA9344.
Specification:
- 560/450/225 MHz (CPU/DDR/AHB)
- 128 MB of RAM (DDR2)
- 8/16 MB of FLASH (SPI NOR)
- 2T2R 2.4G GHz (AR9344)
- 2x 10/100 Mbps Ethernet (PoE support)
- 2x 10/100/1000 Mbps Ethernet
- 7x LED (6 driven by GPIO)
- 1x button (reset)
- 1x DC jack for main power input (9-48 V)
- UART (J23) and LEDs (J2) headers on PCB
Flash instruction (using U-Boot CLI and tftp server):
- Configure PC with static IP 192.168.1.10 and tftp server.
- Rename "sysupgrade" filename to "firmware.bin" and place it in tftp
server directory.
- Connect PC with one of RJ45 ports, power up the board and press
"enter" key to access U-Boot CLI.
- Use the following command to update the device to OpenWrt: "run lfw".
Flash instruction (using U-Boot web-based recovery):
- Configure PC with static IP 192.168.1.xxx(2-254)/24.
- Connect PC with one of RJ45 ports, press the reset button, power up
the board and keep button pressed for around 6-7 seconds, until LEDs
start flashing.
- Open your browser and enter 192.168.1.1, select "sysupgrade" image
and click the upgrade button.
Signed-off-by: 张鹏 <sd20@qxwlan.com>
Qxwlan E750A v4 is based on Qualcomm QCA9344.
Specification:
- 560/450/225 MHz (CPU/DDR/AHB)
- 128 MB of RAM (DDR2)
- 8/16 MB of FLASH (SPI NOR)
- 2T2R 5G GHz (AR9344)
- 2x 10/100 Mbps Ethernet (one port with PoE support)
- 1x miniPCIe slot (USB 2.0 bus only)
- 7x LED (6 driven by GPIO)
- 1x button (reset)
- 1x DC jack for main power input (9-48 V)
- UART (J23) and LEDs (J2) headers on PCB
Flash instruction (using U-Boot CLI and tftp server):
- Configure PC with static IP 192.168.1.10 and tftp server.
- Rename "sysupgrade" filename to "firmware.bin" and place it in tftp
server directory.
- Connect PC with one of RJ45 ports, power up the board and press
"enter" key to access U-Boot CLI.
- Use the following command to update the device to OpenWrt: "run lfw".
Flash instruction (using U-Boot web-based recovery):
- Configure PC with static IP 192.168.1.xxx(2-254)/24.
- Connect PC with one of RJ45 ports, press the reset button, power up
the board and keep button pressed for around 6-7 seconds, until LEDs
start flashing.
- Open your browser and enter 192.168.1.1, select "sysupgrade" image
and click the upgrade button.
Signed-off-by: 张鹏 <sd20@qxwlan.com>
Qxwlan E558 v2 is based on Qualcomm QCA9558 + AR8327.
Specification:
- 720/600/200 MHz (CPU/DDR/AHB)
- 128 MB of RAM (DDR2)
- 8/16 MB of FLASH (SPI NOR)
- 2T2R 2.4 GHz (QCA9558)
- 3x 10/100/1000 Mbps Ethernet (one port with PoE support)
- 4x miniPCIe slot (USB 2.0 bus only)
- 1x microSIM slot
- 5x LED (4 driven by GPIO)
- 1x button (reset)
- 1x 3-pos switch
- 1x DC jack for main power input (9-48 V)
- UART (JP5) and LEDs (J8) headers on PCB
Flash instruction (using U-Boot CLI and tftp server):
- Configure PC with static IP 192.168.1.10 and tftp server.
- Rename "sysupgrade" filename to "firmware.bin" and place it in tftp
server directory.
- Connect PC with one of RJ45 ports, power up the board and press
"enter" key to access U-Boot CLI.
- Use the following command to update the device to OpenWrt: "run lfw".
Flash instruction (using U-Boot web-based recovery):
- Configure PC with static IP 192.168.1.xxx(2-254)/24.
- Connect PC with one of RJ45 ports, press the reset button, power up
the board and keep button pressed for around 6-7 seconds, until LEDs
start flashing.
- Open your browser and enter 192.168.1.1, select "sysupgrade" image
and click the upgrade button.
Signed-off-by: 张鹏 <sd20@qxwlan.com>
The driver is written in such a way that with a board defintion that
connects a fixed phy, mdio, and switch in a certain way, a kernel oops could
result because of lack of previously probed mdio bus.
This commit allows for easier debugging in this case by casting the
correct blame with serial console messages.
Signed-off-by: Daniel F. Dickinson <cshored@thecshore.com>
It's a little noisier but makes it obvious when the ar7240 switch was
connected to the MDIO bus, and to which phy device (or the failure
to do so).
Signed-off-by: Daniel F. Dickinson <cshored@thecshore.com>
NB: Error only appears with ag71xx debug messages and dynamic printk
enabled. This is probably why no one has caught it before.
Previously phy probe debug messages used old (now wrong) functions
to get the phy name for printing. There was also the chance of
a NULL pointer in the event no phy_device was found.
Signed-off-by: Daniel F. Dickinson <cshored@thecshore.com>
With AVM Fritz!Box 4040 and OpenWrt 18.06 RC1 there are many kernel warnings
kern.warn kernel: [87771.917049] ath10k_ahb a000000.wifi: Invalid VHT mcs 15 peer stats
and there are disconnections when the connected clients are many, at the moment I tried with 16 clients on 2.4 GHz and 8 on 5 GHZ.
Firmware 10.4-3.5.3-00057 fixes these warnings and the problem of disconnections of some clients.
Signed-off-by: Massimo Tum <masnia@tiscali.it>
mdio bus isn't a standalone device on ar7240. (and maybe older SoCs?)
Use simple-mfd for ar7241 and later SoCs to get mdio1 ready before gmac0
For ar7240 and older chips, manually create platform device after
ag71xx_hw_init() in ag71xx_probe()to get mdio0 ready between
ag71xx_hw_init() and ag71xx_phy_connect().
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Allow specifying desired mdio clock frequency in dts.
Use default frequency around 5MHz for builtin switch and 2MHz for other mdio bus.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Remove mdio1 and phy1 handle. AR8327N is controlled through mdio0.
Add gmac-config for Archer C7.
Remove ucidef_set_interfaces_lan_wan. They can be determined by config_generate automatically.
The following are for adding support for WDR4900 v2/Archer C7 v1 and other
devices that shared the same machine file in ar71xx:
Move mtd partitions to archer-c7-v2.dts. Only Archer C7 v2 has 16M flash.
Flash on Archer C7 v1/TL-WDR4900 v2 is 8M.
Add label for wlan leds. The default trigger for archer c7/wdr4900 is different.
Move wlan5g led to archer-c7-v2.dts. 5G led on WDR4900 is connected to ar9380.
Move rfkill definition to archer-c7-v2.dts. There is no such a button on wdr4900 v2.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
enable mdio1 by default because mdio1 node is a subnode of eth1
and eth1 node is a "simple-mfd", which makes mdio1 disabled when
eth1 isn't enabled.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Most qca devices use 115200n8 as it's default uart baudrate.
Add 'chosen' node for qca953x like other SoCs in ath79 target.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Commit c7efc93 renamed controller name
to qca,ar9340-intc and added some functions but qca9533.dtsi was overlooked.
Correct the dtsi and adust it to the new format
Add gmac and correct reset for cascaded irq and build-in switch
Also add the reference clock to soc dtsi so we don't have to have it in every dts
Signed-off-by: Lucian Cristian <lucian.cristian@gmail.com>
Remove switch reset definition
Fix gmac compatible string (We only need SW_PHY_SWAP and SW_PHY_ADDR_SWAP on qca953x so use ar9330-gmac instead of ar9340-gmac.)
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
gmac0 is always connected to switch phy4 and mdio1 is always needed.
So add phy handle for eth0 and enable mdio1 by default.
Move fixed-link for gmac1 from device dts to ar9331.dtsi because gmac1 is always connected to builtin switch.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Enable mdio1 by default because mdio1 is needed when eth1 is enabled.
PS: If a ar9341 device has only one port and you only want to use gmac0,
change compatible of gmac1 to "syscon", "simple-mfd" in dts.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
This patch did several things:
1. Probe the builtin switch as a separated mdio device.
2. Register a separated mdio bus for builtin switch.
3. Use generic mdio read/write function instead of calling ag71xx_mdio_mii_read/write directly.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
We need to have mdio1 belonging to gmac1 initialized before gmac0.
Split it into a separated mdio device to get both mdios ready before probing gmac.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
The builtin switch has it's initial valid mac address(00:00:01:00:00:00).
Since the builtin switch is an independent device, setting mac address of gmac1 to builtin switch isn't a good idea and this makes it impossilbe to split builtin switch apart as an independent platform device.
Remove these functions and apply default VLAN during initialization as a preparation for further driver splitting.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Only build images for straight OpenWrt (using all flash; wipes out
partitions that contain information only important for accessing a
now defunct cloud service with the stock firmware) since the stock
firmware is now irrelevant.
Signed-off-by: Daniel F. Dickinson <cshored@thecshore.com>
The wrong MAC addresses (from the point of view of the physical device
label) were being assigned to the wrong interfaces. Fix that.
Signed-off-by: Daniel F. Dickinson <cshored@thecshore.com>
While the stock firmware and previous ar71xx versions of openwrt used the
single ethernet port as a DHCP client, for unmodified openwrt usage it
makes more sense to do the standard openwrt thing and make the ethernet
port a static lan with known address so that users can find the device on
the network more easily.
Signed-off-by: Daniel F. Dickinson <cshored@thecshore.com>
The Skydog cloud service no longer exists hence supporting going back
to stock firmware with cloud support is no longer applicable.
Signed-off-by: Daniel F. Dickinson <cshored@thecshore.com>
The reset button was incorrectly returning KEY_WPS_BUTTON as the key
code. We want KEY_RESTART., so make that fix.
Signed-off-by: Daniel F. Dickinson <cshored@thecshore.com>
The PCIe wireless MAC address address is better labelled as WMAC
than MAC to emphasize that it is for a wireless interface.
Signed-off-by: Daniel F. Dickinson <cshored@thecshore.com>
The CAP324 was an AP for a NaaS offering that is now defunct. While
previously supported in the ar71xx arch, there were some errata (to
be fixed shortly).
Notable differences from ar71xx support:
1) The method of getting the ath9k firmware for the PCIe 2ghz wifi has
changed (due to changes in how the arch handles this), since this device
doesn't use the EEPROM except to get the MAC address of the wifi.
2) /etc/config/wireless will need to be regenerated as the path(s) to
the wireless device(s) have changed.
3) ath79 OpenWrt firmware no longer supports build an image that allows
reverting to stock firmware (as the cloud service no longer exists, the
stock firmware is useless), instead using all of the flash for image and
overlay (less u-boot/env and art).
4) Initial network config treats the ethernet port as a Lan port with
the standard default address (192.168.1.1 unless changed in .config
--e.g. via menuconfig) instead of using DHCP (this was the default for
the stock firmware, however for openwrt use this is rather confusion and
counter-productive as the user has a harder time finding the device on
the network.
Signed-off-by: Daniel F. Dickinson <cshored@thecshore.com>
Add ath79 arch support for PowerCloud Systems CR5000. Previously
supported under ar71xx (however there are some errors in that support;
to be fixed shortly).
Info:
* This board is based on the Atheros DB120 reference design, but doesn't
use the on-board switch. Instead it attachs GMAC0 to an AR8327 switch.
* It only uses GMAC0 and the WAN is simply a VLAN in the stock firmware.
* It has 64MB RAM and 8MB flash.
* In the dts version we get rid of using 'open-drain' for the AR8327
LED controls.
* As with the platform data version we disable JTAG as this conflicts
with one of the pair of GPIO's required for the power/status LED
(GPIO2 and GPIO4 are used for this LED).
* The pcie card wifi has an EEPROM but gets it's MAC address from
the ART partition.
* The SoC wifi (2.4 GHz) is all from the ART.
* The USB is support comes from the SoC.
NB. This is actually an AR9342 rather than AR9344 but we use the 9344
definitions because there are no relevant differences for this board.
NB: Building only images that don't support reverting to the old
cloud-based firmware as the Skydog cloud service for the CR5000 no
longer exists.
Signed-off-by: Daniel F. Dickinson <cshored@thecshore.com>
Update mbedtls to 2.12.0
Multiple security fixes
Add support for Chacha20 and Poly1305 cryptographic primitives and their
associated ciphersuites
Difference in size on mips_24kc (ipk):
164kbytes (167882 bytes)
170kbytes (173563 bytes)
https://tls.mbed.org/tech-updates/releases/mbedtls-2.12.0-2.7.5-and-2.1.14-released
Signed-off-by: Daniel Engberg <daniel.engberg.lists@pyret.net>
81d446b045 introduced incomplete
support for this device.
This patch attempts to correct the situation based on OEM source
code.
LED1-3 are GSM mode on OFW (2G/3G/4G) hence unassigned here.
Signed-off-by: Thibaut VARÈNE <hacks@slashdirt.org>
Tested-by: David Ehrmann <ehrmann@gmail.com>
The active_low flag was missing for the user LED. This LED is open drain
(confirmed in OEM source) and open drain only makes sense for active low
GPIOs.
The two wireless LEDs mentioned in the comments are also #defined for
future reference.
Signed-off-by: Thibaut VARÈNE <hacks@slashdirt.org>
Tested-by: Ryan Mounce <ryan@mounce.com.au>
e15c63a375 introduced code that was trying
to register GPIO 1 as both an LED and a button. The OEM source makes it
clear that LED1 is not wired to the SoC GPIOs. GPIO 1 is the reset button.
Furthermore the (green) power led default state should also be defined,
(matching OEM source), and it should be used by diag.sh since it's
currently the only software-controllable LED.
This patch fixes these issues and renames the corresponding #defines for
clarity
Signed-off-by: Thibaut VARÈNE <hacks@slashdirt.org>
The gpios that control power toggle for USB on the RouterBOARD devices
are active low _off_ switches.
When they are active (low), power is off. When they are inactive
(high), power is on.
Rename GPIO defines, set gpios to GPIOF_ACTIVE_LOW for consistency and
reflect their true action in the display name. This brings openwrt code
in line with OEM.
Signed-off-by: Thibaut VARÈNE <hacks@slashdirt.org>
Tested-by: Ryan Mounce <ryan@mounce.com.au>
