led2l and led2h value is incorrectly set by led3l and led3h.
Bug was introduced in commit: 863e79f8d5
Signed-off-by: Aleksander Jan Bajkowski <A.Bajkowski@stud.elka.pw.edu.pl>
Fixes: 863e79f8d5 ("lantiq: add support for kernel 4.9")
(cherry picked from commit 692390225d)
Refreshed all patches.
New symbol added:
- CONFIG_CIFS_ALLOW_INSECURE_LEGACY
Compile-tested on: cns3xxx, imx6
Runtime-tested on: cns3xxx, imx6
Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
To keep the status of a LED connected to the stp during boot, the get
callback is required. If the callback is missing and the LED default
state is set to keep in the devicetree, the gpio led driver errors out
during load.
Fixes: FS#1620
Signed-off-by: Mathias Kresin <dev@kresin.me>
Refreshed patches. The following patches were upstreamed and have been deleted:
* target/linux/lantiq/patches-4.14/0025-MIPS-lantiq-gphy-Remove-reboot-remove-reset-asserts.patch
* target/linux/generic/pending-4.14/101-clocksource-mips-gic-timer-fix-clocksource-counter-w.patch
* target/linux/generic/pending-4.14/103-MIPS-c-r4k-fix-data-corruption-related-to-cache-coherence.patch
* target/linux/generic/pending-4.14/181-net-usb-add-lte-modem-wistron-neweb-d18q1.patch
Compile-tested: ramips/mt7621, x86/64
Run-tested: ramips/mt7621
Signed-off-by: Stijn Segers <foss@volatilesystems.org>
Backport patch accepted upstream which removes the reset asserts of the
xrx200 gphy driver on reboot/remove.
While doing a global software reset, these bits are not cleared and let
some bootloader fail to initialise the GPHYs. The bootloader don't expect
these bits to be set, as they aren't during power on.
The asserts were a workaround for a wrong syscon-reboot mask. With a mask
set which includes the GPHY resets of the first reset register, the
resets of the second reset register arn't required any more.
Signed-off-by: Mathias Kresin <dev@kresin.me>
During upstreaming the intel phy driver, support for the vr9 v1.1
embedded phys got lost. Backport the upstream send patch adding support
for the vr9 v1.1 embbeded phys to the driver.
Signed-off-by: Mathias Kresin <dev@kresin.me>
cosmetic fixes
Signed-off-by: Mathias Kresin <dev@kresin.me>
This makes some of the mtd patches apply again after some generic
patches were changed.
These problems where found by build bot.
Fixes: ac9bcefa3b ("kernel: use V10 of mtd patchset adding support for "compatible" string")
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
On danube the USB0 registers are at 1e101000 similar to all other lantiq
SoCs.
On Danube and AR9 the USB core is connected to the AHB bus, hence we need
to enable the AHB Bus as well.
Signed-off-by: Mathias Kresin <dev@kresin.me>
Add a custom xrx200 ethernet phy compatible to load the firmware matching
the vr9 revision without specifing an expected revision.
We have quite a few boards in the tree were later produced ones are using
a more recent vr9. It is impossible to distinguish which revision of the
vr9 is used without opening the case and removing a heatsink for some of
them.
Signed-off-by: Mathias Kresin <dev@kresin.me>
This reverts kernel commit 1eed40043579 ("MIPS: smp-mt: Use CPU interrupt
controller IPI IRQ domain support"). With the patch applied, the kernel
hangs during boot if SMP is active.
The Lantiq IRQ controller gets registered first and it directly handles
the MIPS native SW1/2 and HW0 - HW5 IRQs. It looks like this controller
already registers IRQ 0 - 7 and the generic driver only gets the following
IRQs starting later.
The upstream discussion can be found at
https://www.linux-mips.org/archives/linux-mips/2017-05/msg00059.html.
Signed-off-by: Mathias Kresin <dev@kresin.me>
This just copies the patches, configuration and dts files into the
directories hich are used for kernel 4.14.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
