For all SoC in the ath79 target, the PLL controller provides 3 main
clocks "cpu", "ddr" and "ahb" through the input clock "ref".
Signed-off-by: Shiji Yang <yangshiji66@qq.com>
On startup the USB of QCA9531 board can't be initialized successfully.
lsusb result as below:
root@OpenWrt:~# lsusb unable to initialize libusb: -99
This is because usb-phy-analog is not added to reset list.
Signed-off-by: Jinfan Lei <153869379@qq.com>
(added linebreaks and small little changes to the commit message)
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
ar9344_openmesh_mr600-v1.dts:40.10-44.5: Warning (gpios_property):
/leds-ath9k/wifi2g: Missing property '#gpio-cells' in node
/ahb/pcie-controller@180c0000/wifi@0,0 or bad phandle
=> added gpio-controller + #gpio-cells
qca955x_zyxel_nbg6x16.dtsi:121.3-13: Warning (reg_format):
/ahb/usb@1b000000/port@1:reg: property has invalid length (4 bytes)
(#address-cells == 2, #size-cells == 1)
../dts/qca955x_zyxel_nbg6x16.dtsi:131.3-13: Warning (reg_format):
/ahb/usb@1b400000/port@1:reg: property has invalid length (4 bytes)
(#address-cells == 2, #size-cells == 1)
qca955x_zyxel_nbg6x16.dtsi:120.20-123.4: Warning (avoid_default_addr_size):
/ahb/usb@1b000000/port@1: Relying on default #address-cells value
=> ath79's usb-nodes are missing the address- and size-cells properties.
These are needed for usb led trigger support.
ar7242_ubnt_sw.dtsi:54.4-14: Warning (reg_format): /gpio_spi/gpio_spi@0:reg:
property has invalid length (4 bytes) (#address-cells == 1, #size-cells == 1)
=> the #address-cells and #size-cells had to be nudged.
qca9531_dlink_dch-g020-a1.dts:19.6-39.4: Warning (i2c_bus_bridge):
/i2c: incorrect #size-cells for I2C bus
=> #size-cells = <0>;
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
The uart node is enabled on all devices except one (GL-USB150 *).
Thus, let's not have a few hundred nodes to enable it, but do not
disable it in the first place.
Where the majority of devices is using it, also move the serial0
alias to the DTSI.
*) Since GL-USB150 even defines serial0 alias, the missing uart
is probably just a mistake. Anyway, disable it for now so this
patch stays cosmetic.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Specify the device_type property for PCI as well as PCIe controllers.
Otherwise, the PCI range parser will not be selected when using kernel
5.10.
Signed-off-by: David Bauer <mail@david-bauer.net>
ath79.dtsi uses ATH79_CLK_MDIO, so the include
<dt-bindings/clock/ath79-clk.h>
needs to be moved there.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
The QCA9550 family of SoCs have a slightly different reset
sequence compared to older chips.
Normally the bootloader performs this sequence, however
some bootloader implementation expect the operating system
to clear the reset. Also get the PCIe resets from OF to
support the second RC of the QCA9558.
This is required for the AVM FRITZ!WLAN Repeater 1750E to work,
as EVA leaves the PCIe bus in reset.
Tested: AVM FRITZ!WLAN Repeater 1750E - OCEDO Koala
Signed-off-by: David Bauer <mail@david-bauer.net>
A new shift mode was introduced since ar934x which has a way better
performance than current bitbang driver and can handle higher spi
clock properly. This commit adds a new driver to make use of this
new feature.
This new driver has chipselect properly configured and we don't need
cs-gpios hack in dts anymore. Remove them.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
There are several cases where phy-mode and status properties are
set again in DTS(I) files although those were set to the same values
in parent DTSI files already. Remove those cases (and thus also stop
their proliferation by copy/paste).
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
This is the result of grepping/searching for several common
whitespace issues like double empty lines, leading spaces, etc.
This patch fixes them for the ath79 target.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
according to functional block diagram in datasheet, these devices
don't belong to apb bus.
Move these nodes out to match datasheet description.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
With a proper probe deferring for ag71xx we don't need to explicitly
probe mdio1 before gmac0.
Drop all "simple-mfd" in SoC dtsi so that gmac orders can be the same
as ar71xx.
This makes eth0/eth1 order the same as those in ar71xx, which means
we don't need a migration script for this anymore and we can merge
incorrectly split gmac/mdio driver back together.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
According to /arch/mips/include/asm/mach-ath79/ar71xx_regs.h
the size of wmac register range for qca953x is only 0x20000.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
qca9533 is a costdown version of qca9531 which doesn't have USB and PCIE.
Rename the misleading dtsi names and fix the SoC type of gl-ar300m.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
[apply the changes for the gl-x750 as well]
Signed-off-by: Mathias Kresin <dev@kresin.me>
