Drop old cpufreq as now we have new driver that
can use normal kernel opp definition
Tested-by: Stefan Lippers-Hollmann <s.l-h@gmx.de> [nbg6817/ipq8065]
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Rework 0052-PM-OPP-Update-the-voltage-tolerance-when-adjusting-t
to reflect changes upstream.
- Skip unnecessary allocation of buffer to set u_volt
- Change opp u_volt directly
Tested-by: Stefan Lippers-Hollmann <s.l-h@gmx.de> [nbg6817/ipq8065]
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Update 0049-PM-OPP-Support-adjusting-OPP-voltages-at-runtime with
upstream version.
Tested-by: Stefan Lippers-Hollmann <s.l-h@gmx.de> [nbg6817/ipq8065]
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
It has been notice a buf in L2 cache scaling where the scaling is not
done proprely if the frequency is set to the initial state before
the new frequency.
From: https://patchwork.kernel.org/patch/10565443/
* The clocks are set to aux clock rate first to make sure the
* secondary mux is not sourcing off of QSB. The rate is then set to
* two different rates to force a HFPLL reinit under all
* circumstances.
In the initial stage of boot to force a new frequency to apply, is
needed to first set the frequency back to the lowest one (aux_rate)
and then to the target one. This force and make sure the controller
actually switch the frequency to the right one. Apply the same
mechanism to L2 frequency scaling. Before scaling to the target
frequency, first set the frequency to the aux_rate to force the
transition, then scale it to the target frequency. Doing the wrong way
can produce unexpected results and could lock the scaling mechanism
until a full reboot is done (Causing a full reset by the krait-cc driver)
From: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=77612720a2362230af726baa4149c40ec7a7fb05
When the Hfplls are reprogrammed during the rate change,
the primary muxes which are sourced from the same hfpll
for higher frequencies, needs to be switched to the 'safe
secondary mux' as the parent for that small window. This
is done by registering a clk notifier for the muxes and
switching to the safe parent in the PRE_RATE_CHANGE notifier
and back to the original parent in the POST_RATE_CHANGE notifier.
This should apply also to L2 scaling... as we can't relly use
the notifier, we manually do this on L2 scaling.
Tested-by: Stefan Lippers-Hollmann <s.l-h@gmx.de> [nbg6817/ipq8065]
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Deactivate CONFIG_SFP for kernel 4.19 in the generic configuration.
The CONFIG_SFP configuration option was not set to anything in the
ath79 build for me, set it to deactivated by default.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The factory image for the dlink_dir-615-e4 is getting too big which makes
the full ath79 tiny build fail, deactivate it by default.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
The device label contains:
E01: 74:4D:28:xx:xx:30
E05: 74:4D:28:xx:xx:34
The first value corresponds to the address set in hard_config 0x10.
That one is taken for the label MAC address.
Signed-off-by: Sven Roederer <freifunk@it-solutions.geroedel.de>
The node pinctrl0 is already set up in the SOC DTSI files, but
defined again as member of pinctrl in most of the device DTS(I)
files. This patch removes this redundancy for the entire ramips
target.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
VMWare ESXI 6.5 and above is not compatible with
subformat=monolithicSparse (The default qemu-img convert -O VMDK option).
Monolithic Sparse vmdk can be imported, but issues occur when running
sysupgrade with new images and other tasks that modify the file system
(issues like Kernel panics, reboot loops, sometimes crashing the Host ESXI
box).
This change creates an additional VMDK output file for ESXI that sets the
subformat to monlithicFlat, and the adapter_type to the SCSI lsilogic
controller.
This change existed back on:
25e36d379e
But it looks like the change was removed when refactoring occurred with:
5f6a2732f892b6229473576d89cc963ae9c97d5d
Signed-off-by: John Sommerville <jsommerville@untangle.com>
led2l and led2h value is incorrectly set by led3l and led3h.
Bug was introduced in commit: 863e79f8d5
Signed-off-by: Aleksander Jan Bajkowski <A.Bajkowski@stud.elka.pw.edu.pl>
Fixes: 863e79f8d5 ("lantiq: add support for kernel 4.9")
MAC addresses are stored in factory partition at:
0x0004: WiFi 2.4GHz (label_mac +1)
0x0028: LAN, WAN (label_mac)
Signed-off-by: Sungbo Eo <mans0n@gorani.run>
This patch does the following:
- prepend vendor name to model
- set status LEDs to follow the behavior in stock FW
- simplify state_default node definition
- use generic name for flash node
Stock FW status indicators:
https://files.xiaomi-mi.com/files/Mi_Router_Wi-Fi_Nano/Mi_router-NANO_EN.pdf
> Yellow: power on / off
> Blue: during normal operation
> Red: in case of problems with the operation of the device
Signed-off-by: Sungbo Eo <mans0n@gorani.run>
This moves the include of lantiq.dtsi from the DTS files to the
parent falcon_lantiq_easy98000.dtsi.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
This renames lantiq DTS(I) files to follow soc_vendor_device scheme.
This will make DTS files easier to maintain.
As a side effect, DTS file name can be derived from device node
names now, only having to specify a SOC variable in Makefiles.
While at it, move files to arch/mips/boot/dts/lantiq subfolder.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Assign the ASC pins to the serial controller node instead of using pin
hogging (where pins are assigned to the pin controller).
This is the preferred way of assigning pins upstream.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Assign the PCI pins to the PCI controller node instead of using pin
hogging (where pins are assigned to the pin controller).
This is the preferred way of assigning pins upstream.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Assign the STP pins to the STP GPIO controller node instead of using
pin hogging (where pins are assigned to the pin controller).
This is the preferred way of assigning pins upstream.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Assign the GPHY LED pins to the Ethernet controller node instead of
using pin hogging (where pins are assigned to the pin controller).
This is the preferred way of assigning pins upstream.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Assign the NAND pins to the NAND controller node instead of using pin
hogging (where pins are assigned to the pin controller).
This is the preferred way of assigning pins upstream.
While here, define all NAND pins (CLE, ALE, read/RD, ready busy/RDY and
CE/CS1). This means that the pinctrl subsystem knows that these pins are
in use and cannot be re-assigned as GPIOs for example.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Define the SPI pins in the corresponding SoCs.dtsi and assign them to
the SPI controller node. All known boards use CS4 and it's likely that
this is hardcoded in bootrom so this doesn't bother with having
per-board SPI pinmux settings.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Assign the MDIO pins to the switch node instead of using pin hogging
(where pins are assigned to the pin controller).
This is the preferred way of assigning pins upstream.
This converts amazonse, ar9 and vr9. danube is skipped because the pin
controller doesn't define a pinmux for the MDIO pins (some of the SoC
pads may be hardwired to the MDIO pins instead of being configurable).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
This fixes the state_default node by setting the correct groups and
inheriting &state_default from parent DTSI directly.
The compatible for the wifi nodes is changed to the more generic
mediatek,mt76.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
So far, lan/wan MAC address for Edimax RG21S are only read using
mtd_get_mac_ascii, so eth0.1 and eth0.2 addresses are set, but
eth0 address is random. Since the device's LAN address is the same
as for 2.4 GHz, though, this patch set's the eth0 address based
on the 2.4 GHz one, which can be extracted by mtd-mac-address.
This will also allow to move the label MAC address setup to DT.
The setup of lan_mac and wan_mac are kept in 02_network, so those
locations are still in use, too.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
This patch does the following:
- move WiFi LED setup to DTS
- fix LAN/WAN MAC addresses and add label MAC address
- wan5G -> wlan5G, power -> led_power
- increase flash SPI frequency to 30MHz
MAC addresses are stored in Factory partition at:
0x1006: WiFi 2.4GHz, WAN (label_mac)
0x5006: WiFi 5GHz, LAN (label_mac +4)
By improving flash speed,
`time dd if=/dev/mtdblock8 of=/dev/null bs=2k`
is reduced from 7m 10.26s to 5m 9.52s.
Using higher frequencies did not improve speed further.
Signed-off-by: Sungbo Eo <mans0n@gorani.run>
The current ethernet MAC address setup of TL-WDR4300 board is different
from the setup of stock firmware:
OpenWrt: lan = label_mac -2, wan = label_mac -2
stock: lan = label_mac, wan = label_mac +1
This patch applies to all devices using TL-WDR4300 board:
TL-WDR3600 v1
TL-WDR4300 v1
TL-WDR4300 v1 (IL)
TL-WDR4310 v1
Mercury MW4530R v1
Signed-off-by: Sungbo Eo <mans0n@gorani.run>
The current ethernet MAC address setup of TL-WDR4300 board is different
from the setup of stock firmware:
OpenWrt: lan = label_mac -2, wan = label_mac -2
stock: lan = label_mac, wan = label_mac +1
The full address assignment is as follows:
LAN label
WAN label + 1
5G label
2G label - 1
This patch changes all devices using TL-WDR4300 board:
TL-WDR3600 v1 (checked on device)
TL-WDR4300 v1 (checked on device)
TL-WDR4300 v1 (IL)
Signed-off-by: Sungbo Eo <mans0n@gorani.run>
[rephrase/extend commit title/message]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Hardware
--------
SoC: Qualcomm IPQ4029
RAM: 512M DDR3
FLASH: - 128MB NAND (Macronix MX30LF1G18AC)
- 4MB SPI-NOR (Macronix MX25R3235F)
TPM: Atmel AT97SC3203
BLE: Texas Instruments CC2540T
attached to ttyMSM0
ETH: Atheros AR8035
LED: WiFi (amber / green)
System (red / green)
BTN: Reset
To connect to the serial console, you can solder to the labled pads next
to the USB port or use your Aruba supplied UARt adapter.
Do NOT plug a standard USB cable into the Console labled USB-port!
Aruba/HPE simply put UART on the micro-USB pins. You can solder yourself
an adapter cable:
VCC - NC
D+ - TX
D- - RX
GND - GND
The console setting in bootloader and OS is 9600 8N1. Voltage level is
3.3V.
To enable a full list of commands in the U-Boot "help" command, execute
the literal "diag" command.
Installation
------------
1. Get the OpenWrt initramfs image. Rename it to ipq40xx.ari and put it
into the TFTP server root directory. Configure the TFTP server to
be reachable at 192.168.1.75/24. Connect the machine running the TFTP
server to the ethernet port of the access point.
2. Connect to the serial console. Interrupt autobooting by pressing
Enter when prompted.
3. Configure the bootargs and bootcmd for OpenWrt.
$ setenv bootargs_openwrt "setenv bootargs console=ttyMSM1,9600n8"
$ setenv nandboot_openwrt "run bootargs_openwrt; ubi part aos1;
ubi read 0x85000000 kernel; bootm 0x85000000"
$ setenv ramboot_openwrt "run bootargs_openwrt;
setenv ipaddr 192.168.1.105; setenv serverip 192.168.1.75;
netget; set fdt_high 0x87000000; bootm"
$ setenv bootcmd "run nandboot_openwrt"
$ saveenv
4. Load OpenWrt into RAM:
$ run ramboot_openwrt
5. After OpenWrt booted, transfer the OpenWrt sysupgrade image to the
/tmp folder on the device.
6. Flash OpenWrt:
$ ubidetach -p /dev/mtd1
$ ubiformat /dev/mtd1
$ sysupgrade -n /tmp/openwrt-sysupgrade.bin
To go back to the stock firmware, simply reset the bootcmd in the
bootloader to the original value:
$ setenv bootcmd "boot"
$ saveenv
Signed-off-by: David Bauer <mail@david-bauer.net>
Device support for Belkin F9K1109v1 was added using set_usb_led()
although this was removed in 772b27c207 ("ramips: set F5D8235 v1
usb led trigger via devicetree").
Use ucidef_set_led_usbport() instead.
Fixes: f2c83532f9 ("ramips: add support for Belkin F9K1109v1")
Signed-off-by: Sungbo Eo <mans0n@gorani.run>
[rephrase commit title and message]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
This harmonizes the line wrapping in image Makefile device
definitions, as those are frequently copy-pasted and are a common
subject of review comments. Having the treatment unifying should
reduce the cases where adjustment is necessary afterwards.
Harmonization is achieved by consistently (read "strictly")
applying certain rules:
- Never put more than 80 characters into one line
- Fill lines up (do not break after 40 chars because of ...)
- Use one tab for indent after wrapping by "\"
- Only break after pipe "|" for IMAGE variables
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
This harmonizes the line wrapping in image Makefile device
definitions, as those are frequently copy-pasted and are a common
subject of review comments. Having the treatment unifying should
reduce the cases where adjustment is necessary afterwards.
Harmonization is achieved by consistently (read "strictly")
applying certain rules:
- Never put more than 80 characters into one line
- Fill lines up (do not break after 40 chars because of ...)
- Use one tab for indent after wrapping by "\"
- Only break after pipe "|" for IMAGE variables
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
This enables using 4kiB sectors as erase blocks for 4MiB NOR flash ICs
that support it.
Writeable jffs2 overlay used to store settings requires a partition with
at least 5 erase blocks, so using small sectors is essential for devices
with 4MiB flash.
Sysupgrading a device running firmware without this feature will likely
not allow to preserve configs automatically but since ath79 is
considered to be in a "technology preview" state it shouldn't be a
problem.
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
