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lantiq: dts: assign the NAND pins to the nand-controller node
Assign the NAND pins to the NAND controller node instead of using pin hogging (where pins are assigned to the pin controller). This is the preferred way of assigning pins upstream. While here, define all NAND pins (CLE, ALE, read/RD, ready busy/RDY and CE/CS1). This means that the pinctrl subsystem knows that these pins are in use and cannot be re-assigned as GPIOs for example. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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7298c25f74
@ -108,19 +108,6 @@
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pinctrl-0 = <&state_default>;
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state_default: pinmux {
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nand_out {
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lantiq,groups = "nand cle", "nand ale";
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lantiq,function = "ebu";
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lantiq,output = <1>;
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lantiq,open-drain = <0>;
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lantiq,pull = <0>;
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};
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nand_cs1 {
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lantiq,groups = "nand cs1";
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lantiq,function = "ebu";
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lantiq,open-drain = <0>;
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lantiq,pull = <0>;
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};
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exin {
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lantiq,groups = "exin1";
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lantiq,function = "exin";
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@ -209,6 +196,9 @@
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reg = <1 0x0 0x2000000 >;
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req-mask = <0x1>; /* PCI request lines to mask during NAND access */
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pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;
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pinctrl-names = "default";
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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@ -109,20 +109,6 @@
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pinctrl-0 = <&state_default>;
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state_default: pinmux {
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nand_out {
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lantiq,groups = "nand cle", "nand ale";
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lantiq,function = "ebu";
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lantiq,output = <1>;
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lantiq,open-drain = <0>;
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lantiq,pull = <0>;
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};
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nand_cs1 {
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lantiq,groups = "nand cs1";
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lantiq,function = "ebu";
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lantiq,open-drain = <0>;
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lantiq,pull = <0>;
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};
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pci_in {
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lantiq,groups = "req1";
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lantiq,function = "pci";
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@ -158,6 +144,9 @@
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reg = <1 0x0 0x2000000 >;
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req-mask = <0x1>; /* PCI request lines to mask during NAND access */
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pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;
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pinctrl-names = "default";
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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@ -214,19 +214,6 @@
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lantiq,open-drain = <0>;
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lantiq,output = <1>;
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};
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nand_out {
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lantiq,groups = "nand cle", "nand ale";
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lantiq,function = "ebu";
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lantiq,output = <1>;
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lantiq,open-drain = <0>;
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lantiq,pull = <0>;
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};
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nand_cs1 {
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lantiq,groups = "nand cs1";
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lantiq,function = "ebu";
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lantiq,open-drain = <0>;
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lantiq,pull = <0>;
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};
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};
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};
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@ -236,6 +223,10 @@
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lantiq,cs = <1>;
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bank-width = <2>;
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reg = <0x1 0x0 0x2000000>;
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pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;
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pinctrl-names = "default";
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nand-on-flash-bbt;
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nand-ecc-strength = <3>;
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nand-ecc-step-size = <256>;
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@ -193,18 +193,12 @@
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lantiq,groups = "stp";
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lantiq,function = "stp";
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};
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nand {
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lantiq,groups = "nand cle", "nand ale",
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"nand rd", "nand rdy";
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lantiq,function = "ebu";
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};
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pci {
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lantiq,groups = "gnt1", "req1";
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lantiq,function = "pci";
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};
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conf_out {
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lantiq,pins = "io24", "io13", "io49", /* nand cle, ale and rd */
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"io4", "io5", "io6", /* stp */
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lantiq,pins = "io4", "io5", "io6", /* stp */
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"io21",
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"io33";
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lantiq,open-drain;
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@ -217,8 +211,7 @@
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lantiq,output = <1>;
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};
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conf_in {
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lantiq,pins = "io39", /* exin3 */
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"io48"; /* nand rdy */
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lantiq,pins = "io39"; /* exin3 */
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lantiq,pull = <2>;
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};
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};
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@ -19,6 +19,9 @@
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bank-width = <2>;
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reg = <0 0x0 0x2000000>;
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pinctrl-0 = <&nand_pins>;
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pinctrl-names = "default";
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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@ -13,6 +13,9 @@
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bank-width = <2>;
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reg = <1 0x0 0x2000000>;
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pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;
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pinctrl-names = "default";
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nand-ecc-mode = "soft";
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nand-ecc-strength = <3>;
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nand-ecc-step-size = <256>;
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@ -13,6 +13,9 @@
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bank-width = <2>;
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reg = <1 0x0 0x2000000>;
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pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;
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pinctrl-names = "default";
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nand-ecc-mode = "on-die";
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partitions {
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@ -193,13 +193,6 @@
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pinctrl-0 = <&state_default>;
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state_default: pinmux {
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nand {
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lantiq,groups = "nand cle", "nand ale",
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"nand rd", "nand cs1", "nand rdy";
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lantiq,function = "ebu";
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lantiq,pull = <1>;
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};
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phy-rst {
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lantiq,pins = "io37", "io44";
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lantiq,pull = <0>;
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@ -36,12 +36,6 @@
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};
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&state_default {
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nand {
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lantiq,groups = "nand ale", "nand cle",
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"nand cs1", "nand rd", "nand rdy";
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lantiq,function = "ebu";
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};
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pcie-rst {
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lantiq,pins = "io21";
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lantiq,open-drain = <1>;
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@ -85,6 +79,10 @@
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lantiq,cs1 = <1>;
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bank-width = <1>;
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reg = <1 0x0 0x2000000>;
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pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;
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pinctrl-names = "default";
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nand-ecc-mode = "on-die";
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partitions {
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@ -89,6 +89,9 @@
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reg = <0 0x0 0x2000000>;
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lantiq,cs = <1>;
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pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;
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pinctrl-names = "default";
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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@ -172,16 +175,6 @@
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lantiq,open-drain = <1>;
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lantiq,output = <1>;
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};
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nand-mux {
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lantiq,groups = "nand cle", "nand ale",
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"nand rd", "nand cs1",
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"nand rdy";
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lantiq,function = "ebu";
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};
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nand-pins {
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lantiq,pins = "io13", "io24", "io49";
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lantiq,pull = <1>;
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};
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};
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};
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@ -30,6 +30,9 @@
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bank-width = <2>;
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reg = <0 0x0 0x2000000>;
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pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;
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pinctrl-names = "default";
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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@ -21,6 +21,9 @@
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bank-width = <2>;
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reg = <0 0x0 0x800000>;
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pinctrl-0 = <&nand_pins>, <&nand_cs1_pins>;
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pinctrl-names = "default";
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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@ -242,19 +242,6 @@
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lantiq,open-drain = <0>;
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lantiq,output = <1>;
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};
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nand_out {
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lantiq,groups = "nand cle", "nand ale";
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lantiq,function = "ebu";
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lantiq,output = <1>;
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lantiq,open-drain = <0>;
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lantiq,pull = <0>;
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};
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nand_cs1 {
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lantiq,groups = "nand cs1";
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lantiq,function = "ebu";
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lantiq,open-drain = <0>;
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lantiq,pull = <0>;
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};
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};
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};
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@ -178,6 +178,32 @@
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};
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};
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nand_pins: nand {
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mux-0 {
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lantiq,groups = "nand cle", "nand ale",
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"nand rd";
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lantiq,function = "ebu";
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lantiq,output = <1>;
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lantiq,open-drain = <0>;
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lantiq,pull = <0>;
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};
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mux-1 {
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lantiq,groups = "nand rdy";
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lantiq,function = "ebu";
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lantiq,output = <0>;
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lantiq,pull = <2>;
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};
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};
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nand_cs1_pins: nand-cs1 {
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mux {
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lantiq,groups = "nand cs1";
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lantiq,function = "ebu";
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lantiq,open-drain = <0>;
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lantiq,pull = <0>;
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};
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};
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spi_pins: spi {
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mux-0 {
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lantiq,groups = "spi_di";
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@ -162,6 +162,32 @@
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#gpio-cells = <2>;
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gpio-controller;
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reg = <0xe100b10 0xa0>;
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nand_pins: nand {
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mux-0 {
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lantiq,groups = "nand cle", "nand ale",
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"nand rd";
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lantiq,function = "ebu";
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lantiq,output = <1>;
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lantiq,open-drain = <0>;
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lantiq,pull = <0>;
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};
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mux-1 {
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lantiq,groups = "nand rdy";
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lantiq,function = "ebu";
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lantiq,output = <0>;
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lantiq,pull = <2>;
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};
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};
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nand_cs1_pins: nand-cs1 {
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mux {
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lantiq,groups = "nand cs1";
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lantiq,function = "ebu";
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lantiq,open-drain = <0>;
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lantiq,pull = <0>;
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};
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};
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};
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asc1: serial@e100c00 {
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@ -220,6 +220,32 @@
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};
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};
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nand_pins: nand {
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mux-0 {
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lantiq,groups = "nand cle", "nand ale",
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"nand rd";
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lantiq,function = "ebu";
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lantiq,output = <1>;
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lantiq,open-drain = <0>;
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lantiq,pull = <0>;
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};
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mux-1 {
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lantiq,groups = "nand rdy";
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lantiq,function = "ebu";
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lantiq,output = <0>;
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lantiq,pull = <2>;
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};
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};
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nand_cs1_pins: nand-cs1 {
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mux {
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lantiq,groups = "nand cs1";
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lantiq,function = "ebu";
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lantiq,open-drain = <0>;
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lantiq,pull = <0>;
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};
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};
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spi_pins: spi {
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mux-0 {
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lantiq,groups = "spi_di";
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