Commit Graph

465 Commits

Author SHA1 Message Date
Sander Vanheule
039e5be4af realtek: remove RTL839x path in RTL838x multicast
The multicast setup function rtl838x_eth_set_multicast_list() checks if
the current SoC is a RTL839x family device. However, the function is
only included in the RTL838x ops table, so this path should never be
taken, making this dead code. rtl839x_eth_set_multicast_list() is
already present in the RTL839x ops table, so it should be safe to remove
this branch.

While touching the code, also re-sort the functions to match sorting
elsewhere, with rtl838x coming before rtl839x.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-10-23 22:33:08 +02:00
Jan Hoffmann
19b86658b7 realtek: reduce excessive logging for FDB operations
Currently several messages at KERN_INFO level are printed for every FDB
del/dump operation. This can cause a significant slowdown for example
while using "bridge fdb", and may even trigger a watchdog.

Remove most of these log messages, as the new L2 table debugfs node
should be a good replacement. Change the remaining messages to
KERN_DEBUG level.

Signed-off-by: Jan Hoffmann <jan@3e8.eu>
2022-10-23 22:33:08 +02:00
Jan Hoffmann
ae9487c535 realtek: add debugfs node for L2 table
This allows to view all unicast and multicast entries that are currently
in the L2 hash table and the CAM.

Signed-off-by: Jan Hoffmann <jan@3e8.eu>
2022-10-23 22:33:08 +02:00
Jan Hoffmann
4657a5301e realtek: avoid busy waiting for RTL839x PHY read/write
Switch to a polling implementation similar to the one for RTL838x, to
allow other kernel tasks to run while waiting.

Signed-off-by: Jan Hoffmann <jan@3e8.eu>
2022-10-23 22:33:08 +02:00
Markus Stockhausen
b295c7140b realtek: disable otto timer for RTL93xx targets
The new timer is not yet ready for all targets. Avoid interactive
questions during build

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[rename symbol to CONFIG_REALTEK_OTTO_TIMER]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-10-23 22:33:08 +02:00
Markus Stockhausen
beb5b07943 realtek: timer driver: activate for RTL839X devices
Use the	new timer driver for the RTL839X devices and remove the
no longer needed modules.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[correct timer compatible order, update selected symbols]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-10-23 22:33:08 +02:00
Markus Stockhausen
ec675fb744 realtek: timer driver: activate for RTL838X devices
Use the new timer driver for the RTL838X devices. Remove the no
longer needed modules.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[correct timer compatible order, update selected symbols]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-10-23 22:33:08 +02:00
Markus Stockhausen
5c677b2298 realtek: timer driver: documentation
Provide some helpful information about the devicetree configuration of
our new driver

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[correct compatible order in examples]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-10-23 22:33:08 +02:00
Markus Stockhausen
3cc8011171 realtek: resurrect timer driver
Now that we provide a clock driver for the Reltek SOCs the CPU frequency might
change on demand. This has direct visible effects during operation

- the CEVT 4K timer is no longer a stable clocksource
- after CPU frequencies changes time calculation works wrong
- sched_clock falls back to kernel default interval (100 Hz)
- timestamps in dmesg have only 2 digits left

[    0.000000] sched_clock: 32 bits at 100 Hz, resolution 10000000ns, wraps ...
[    0.060000] pid_max: default: 32768 minimum: 301
[    0.070000] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
[    0.070000] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
[    0.080000] dyndbg: Ignore empty _ddebug table in a CONFIG_DYNAMIC_DEBUG_CORE build
[    0.090000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, ...

Looking around where we can start the CEVT timer for RTL930X is a good basis.
Initially it was developed as a clocksource driver for the broken timer in that
specific SOC series. Afterwards it was shifted around to the CEVT location,
got SMP enablement and lost its clocksource feature. So we at least have
something to copy from. As the timers on these devices are well understood
the implementation follows this way:

- leave the RTL930X implementation as is
- provide a new driver for RTL83XX devices only
- swap RTL930X driver at a later time

Like the clock driver this patch contains a self contained module that is SOC
independet and already provides full support for the RTL838X, RTL839X and
RTL930X devices. Some of the new (or reestablished) features are:

- simplified initialization routines
- SMP setup with CPU hotplug framework
- derived from LXB clock speed
- supplied clocksource
- dedicated register functions for better readability
- documentation about some caveats

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[remove unused header includes, remove old CONFIG_MIPS dependency, add
REALTEK_ prefix to driver symbol]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-10-23 22:33:08 +02:00
INAGAKI Hiroshi
629f2de1a7 realtek: cleanup rtl83{8x,9x}_enable_learning/flood
In *_enable_learning() only address learning should be configured, so
remove enabling forwarding. Forwarding is configured by the respective
*_enable_flood() functions.

Clean up both functions for RTL838x and RTL839x, and fix the comment on
the number of entries.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[squash RTL838x, RTL839x changes]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-10-08 11:05:03 +02:00
INAGAKI Hiroshi
b11b56e8a8 realtek: swap *_phylink_mac_link_down() contents
Fix the (accidentally?) swapped contents of
rtl83xx_phylink_mac_link_down() and rtl93xx_phylink_mac_link_down().

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[amend commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-10-08 11:05:02 +02:00
INAGAKI Hiroshi
ff307f52f5 realtek: fix place of fdb/mdb info messages
Those messages should be printed when entry was found (idx >= 0). Move
them to the right place to not print invalid entry indices.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[amden commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-10-08 11:05:02 +02:00
INAGAKI Hiroshi
3834e72fa3 realtek: add missing of.h include in phy driver
of.h is required for of_property_read_u32().

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[amend commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-10-08 11:05:02 +02:00
INAGAKI Hiroshi
04cca345df realtek: fix use of uninitialized sds_mode
The initial state of sds_mode in rtl9300_force_sds_mode() is null and it
will be configured in switch-case. So print message after it.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[amend commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-10-08 11:05:02 +02:00
INAGAKI Hiroshi
27a580df4a realtek: use MIPS fw_init_cmdline()
Use the generic function of MIPS in Linux Kernel instead of open coding
our own initialisation.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[amend commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-10-08 11:05:02 +02:00
INAGAKI Hiroshi
5b37e3245d realtek: update SMP-related calls in prom_init()
The availabibity of probing CPC depends on CONFIG_MIPS_CPC symbol and it
will be checked in arch/mips/include/asm/mips-cpc.h. RTL9310 selects
this symbol, so the family check is redudant.

Furthermore, mips_cm_probe() is already called from setup_arch() in
mips/kernel/setup.c before prom_init(), and as such is not required.

Also move mips_cpc_probe() to run just before registering SMP ops.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
[squash SMP change commits, reword commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
---
This patch only really has an impact on the rtl931x subtarget, which has
no devices. Noboby is currently set up to test these patches either, but
the end result is closer to MIPS_GENERIC, so I do not expect it to cause
issues.
2022-10-08 11:05:02 +02:00
INAGAKI Hiroshi
9b53a29a58 realtek: separate lock of RTL8231 from phy driver
RTL8231 and ethernet phys are not on the same bus, so separate the lock
to each own to cut off the unnecessary dependency.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2022-10-08 11:05:02 +02:00
John Audia
eed0a31b90 kernel: bump 5.10 to 5.10.146
All patches automatically rebased.

Signed-off-by: John Audia <therealgraysky@proton.me>
2022-10-02 20:21:55 +02:00
Sander Vanheule
918e774658 realtek: use correct CAUSEF_DC macro in prom.c
The workaround for an already-enabled R4K timer used a non-existent
macro CAUSE_DC. Fix compiling by using the actual macro CAUSEF_DC.

Fixes: b7aab19585 ("realtek: SMP handling of R4K timer interrupts")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-10-01 09:56:54 +02:00
Markus Stockhausen
b7aab19585 realtek: SMP handling of R4K timer interrupts
Until now there has been no good explanation why we mess with the R4K
timer on SMP. After extensive testing and looking at the SDK code it
becomes clear what it is all about.

When we disable the CEVT_R4K module (we will do with the new timer
driver) the R4K timer hardware still fires interrupts on the secondary
CPU. To get around this we have two options:

- Disable IRQ 7
- Stop the counter completely

This patch selects option two because this is the root of evil.. To be
on the safe side we will do it only in case the CEVT_R4K module is
disabled.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-10-01 09:22:32 +02:00
Markus Stockhausen
2b12da1313 realtek: fix SMP startup
The scope of the SMP startup structure is wrong. It is created on the
stack and not as a global variable. This can lead to startup failures.

Fixes: 3f41360eb7 ("realtek: use upstream recommendation for CPU start")
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de
2022-10-01 09:22:32 +02:00
Olliver Schinagl
f1f97db627
realtek: Convert incorrect v5.10 patches
OpenWRT's developer guide prefers having actual patches so they an be
sent upstream more easily.

However, in this case, Adding proper fields also allows for `git am` to
properly function. Some of these patches are quite old, and lack much
traceable history.

This commit tries to rectify that, by digging in the history to find
where and how it was first added.

It is by no means perfect and also shows some patches that should have
been long gone.

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
2022-10-01 02:47:57 +02:00
Felix Fietkau
36f2ab4bfd kernel: move kernel image cmdline hack to the octeon target
It is the only remaining user of this hack

Signed-off-by: Felix Fietkau <nbd@nbd.name>
2022-09-30 13:13:51 +02:00
Christian Marangi
165b66d910
realtek: rtl931x: fix missing CONFIG_COMMON_CLK_REALTEK config flag
When the realtek clock driver was introduced, CONFIG_COMMON_CLK_REALTEK
was not correctly disabled for other subtarget. Add the missing config
flag to fix compilation error on buildbot.

Fixes: 4850bd887c ("realtek: add RTL83XX clock driver")
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2022-09-28 01:15:47 +02:00
Jan Hoffmann
d924a75be3 realtek: fix RTL839x egress tag for ports >= 32
Don't overwrite AS_DPM and L2LEARNING flags when dest_port is >= 32.

Fixes: 1773264a0c ("realtek: correct egress frame port verification")
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
2022-09-25 20:53:24 +02:00
John Audia
eff4f8b2f0 kernel: bump 5.10 to 5.10.144
All patches automatically rebased.

Signed-off-by: John Audia <therealgraysky@proton.me>
2022-09-22 12:46:55 +02:00
Markus Stockhausen
3f41360eb7 realtek: use upstream recommendation for secondary CPU start
Currently we fix interrupts/timers for the secondary CPU by patching
vsmp_init_secondary(). Get a little bit more generic and use the
upstream recommended way instead. Additionally avoid a check around
register_cps_smp_ops() because it does that itself.

See https://lkml.org/lkml/2022/9/12/522

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-09-18 20:38:56 +02:00
Markus Stockhausen
bcb5d6b21b realtek: avoid wrong interrupt routing
The interrupt controller depends on two control registers. GIMR enables
or disables interrupts and IRRx routes these to MIPS CPU interrupts 2-7.
Wiki currently states "A value of '0' (in IRRx) disconnects this input from
the output line, independent of the line's setting in GIMR."

Contrary to normal intuition this statement DOES NOT mean, that interrupts
can be disabled by IRRx alone. The sad truth was discovered by enabling
SMP for an Zyxel XGS1010 on the 930x target. It shows that driver and
interrupts behave as follows:

- Timer 0 interrupt 7 has active routing to CPU0 and no routing to CPU1
- Timer 1 interrupt 8 has no routing to CPU0 and active routing to CPU1
- Unmasking (enabling) interrupts writes 1 bits to all GIMR registers
- Masking (disabling) interrupts writes 0 bits to both GIMR registers

During operation we can encounter a situation like

- GIMR bit for a interrupt/CPU combination is set to enabed (=1)
- IRRx routing bits for a interrupt/CPU combination are set to disabed (=0)

This setting already allows the hardware to fire interrupts to the target
CPU/VPE if the other CPU/VPE is currently busy. Especially for CPU bound
timer interrupts this is lethal. If timer interrupt 7 arrives at CPU1 and
vice versa for interrupt 8 the restart trigger gets lost. The timer dies
and a msleep() operation in the kernel will halt endlessly.

Fix this by tracking the IRRx active routing setting in a new bitfield with
0="routing active" and 1="no routing". Enable interrupts in GIMR only
for a interrupt & CPU if routing is active. Thus we have

- GIMR = 0 / IRRx = 0 -> everything disabled
- GIMR = 1 / IRRx > 0 -> active and normal routing
- GIMR = 0 / IRRx > 0 -> masked (disabled) with normal routing
- GIMR = 1 / IRRx = 0 -> no longer possible

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-09-18 20:38:56 +02:00
Sander Vanheule
fe5a2f334f realtek: use Device prefix for common recipes
The Build prefix is used for image build commands, while the Device
prefix should be used for base recipes for devices. Apply the same
naming convention here.

While touching the file, also fix the mixed indentation.

Suggested-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-09-18 10:12:19 +02:00
Olliver Schinagl
d2fa68379f realtek: move Netgear recipe to subtarget Makefile
There seems to be no reason to have the Netgear switches as part of
the main Makefile. Move it to its subtarget-specific Makefile since
it is only applicable there.

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
[update commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-09-17 22:27:32 +02:00
Sander Vanheule
51ecfb086c realtek: move hpe_1920 recipe to common.mk
Currently supported HPE 1920 devices all have an RTL838x SoC, but there
are larger switches with RTL839x SoCs, although currently not supported.
Move the build recipe to common.mk so the larger devices can also make
use of the recipe, while moving it out of the main Makefile.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-09-17 22:20:32 +02:00
Sander Vanheule
9338c09ecb realtek: merge duplicated DGS-1210 recipes
The D-Link DGS-1210 device series currently has supported devices with
both RTL838x and RTL839x SoCs. An image build recipe has been defined in
both subtarget makefiles, but these are mostly identical, save for the
SOC variable.

Move the SOC variable from the DGS-1210 build recipes to the applicable
devices, and put the remaining duplicate code in a shared Makefile.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-09-17 22:12:35 +02:00
Markus Stockhausen
e04e821471 realtek: add support for DGS-1210-52
Hardware specification
----------------------

* RTL8393M SoC, 1 MIPS 34Kc core @ 700MHz
* 128MB DRAM
* 32MB NOR Flash
* 48 x 10/100/1000BASE-T ports
  - 6 x External PHY with 8 ports (RTL8218D)
* 4 x Gigabit RJ45/SFP Combo ports
  - External PHY with 4 SFP ports (RTL8214FC)
* Power LED
* Reset button on front panel
* UART (115200 8N1) via unpopulated standard 0.1" pin header marked J14

The gpio-restart node is not required but it does reset the switch.

TODO: The 4 combo ports attached to the RTL8214FC are not detect
properly. Linux kernel reports 49 and 50 as "External RTL8393 SERDES"
and 51 and 52 as "RTL8218B (external)". Those ports only work if
u-boot initialize it (for example, loading initramfs image using one
of those ports). A patch to PHY detection is needed for full support.

The firmware recovery using U-Boot is broken for all DGS-1210 tested
devices as pressing RESET does not trigger it (only if pressed from a
running stock image)

UART pinout
-----------

[o]ooo|J14
 | ||`------ GND
 | |`------- RX
 | `-------- TX
 `---------- Vcc (3V3)

Installation using OEM upgrade
------------------------------

1. Make sure you are running OEM firmware in image2 slot (logged as admin):
   - > config firmware image_id 2 boot_up
   - > reboot
2. Install squashfs-factory_image1.bin to image1 using (logged as admin):
   - > download firmware_fromTFTP <tftpserver> factory_image1.bin
   - > config firmware image_id 1 boot_up
   - > reboot

Installation using serial interface
-----------------------------------

1. Press Escape key during `Hit Esc key to stop autoboot` prompt
2. Press CTRL+C keys to get into real U-Boot prompt
3. Init network with `rtk network on` command
4. Load image with `tftpboot 0x8f000000 openwrt-realtek-rtl839x-d-link_dgs-1210-52-initramfs-kernel.bin` command
5. Boot the image with `bootm` command

Once booted the initramfs, install the squashfs-sysupgrade.bin as a
normal OpenWrt system.

Dual-boot with stock firmware using writable u-boot-env
-------------------------------------------------------

From stock to OpenWrt / boot image 1 (CLI as admin):
   - > config firmware image_id 1 boot_up
   - > reboot

From OpenWrt to stock / boot image 2: (shell as root)
   - # fw_setenv bootcmd 'run addargs ; bootm 0xb4e80000'
   - # fw_setenv image '/dev/mtdblock7'
   - # reboot

Debrick using serial interface
------------------------------

1. Press Escape key during `Hit Esc key to stop autoboot` prompt
2. In a Windows PC, run 'D-Link Network Assistant v2.0.2.4'. It should
   detect the switch
3. Flash the firmware.

Back to stock firmware using dual-boot
--------------------------------------

If you have serial interface, you can change u-boot env vars
interrupting the boot process. If not but you are running OpenWrt, you
can dual-boot (as mentioned eariler) and skip to step 4:

1. Press Escape key during `Hit Esc key to stop autoboot` prompt
2. Press CTRL+C keys to get into real U-Boot prompt
3. Boot the image 2:
   - set image /dev/mtdblock7; run addargs; bootm 0xb4e80000
4. Once booted, log as admin and change the boot image to 2
   - > config firmware image_id 2 boot_up
   - > reboot
5. After the boot, flash image1 with the vendor image

Back to stock firmware using DNA
--------------------------------

1. From an OpenWrt:
   - # fw_setenv bootstop on
   - # reboot
2. In a Windows PC, run 'D-Link Network Assistant v2.0.2.4'. It should
   detect the switch
3. Flash the firmware.

It has been developed and tested on device with F3 revision.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
2022-09-17 21:28:21 +02:00
Markus Stockhausen
9ed1a1138e realtek: align DT macros in RTL839X with RTL838X
Add a missing definition to the RTL839X DT.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-09-17 21:28:21 +02:00
Markus Stockhausen
307e5cfc6e realtek: D-Link make common DT include generic
The D-Link DGS device tree was reorganized to better reflect the common
DT parts. The common include is named SOC specific (838X) and it seemed
like a good choice to add another common include in the future for the
RTL839X devices. From the current point of view this option is not really
needed.

1. The common part only includes data that matches RTL839X devices too.
2. The Panasonic DT structure avoids including the basic DTSI inside the
   common DTSI.

Taking simplicity of the Panasonic include logic and in perparation to
provide DGS-1210-52 support it makes sense to harmonize this.

- rename common include to reflect its content
- move the link to the root DTSI directly to the device specific DTS

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-09-17 21:28:21 +02:00
Olliver Schinagl
c4d030f24c
realtek: rtl838x: Fix ethernet polling timeout on probe
Due to an oversight we accidentally inverted the timeout check. This
patch corrects this.

Fixes: 9cec4a0ea4 ("realtek: Use built-in functionality for timeout loop")
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
[ wrap poll_timeout line to 80 char ]
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2022-09-14 18:23:06 +02:00
Olliver Schinagl
9cec4a0ea4
realtek: Use built-in functionality for timeout loop
In commit 81e3017609 ("realtek: clean up rtl838x MDIO busy wait loop")
a hand-crafted loop was created, that nearly exactly replicate the
iopoll's `read_poll_timeout` functionality.

Use that instead.

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
2022-09-14 12:03:57 +02:00
Alexandru Gagniuc
01e2184c49 realtek: add support for TP-Link SG2210P
Add support for the TP-Link SG2210P switch. This is an RTL8380 based
switch with eight RJ-45 ports with 802.3af PoE, and two SFP ports.

This device shares the same board with the SG2008P and SG2008. To
model this, declare all the capabilities in the sg2xxx dtsi, and
disable unpopulated on the lower end models.

Specifications:
---------------
 - SoC:       Realtek RTL8380M
 - Flash:     32 MiB SPI flash (Vendor varies)
 - RAM:	      256 MiB (Vendor varies)
 - Ethernet:  8x 10/100/1000 Mbps with PoE (all ports)
              2x SFP ports
 - Buttons:   1x "Reset" button on front panel
 - Power:     53.5V DC barrel jack
 - UART:      1x serial header, unpopulated
 - PoE:       2x TI TPS23861 I2C PoE controller

Works:
------
  - (8) RJ-45 ethernet ports
  - (2) SFP ports (with caveats)
  - Switch functions
  - System LED

Not yet enabled:
----------------
  - Power-over-Ethernet (driver works, but doesn't enable "auto" mode)
  - PoE LEDs

Enabling SFP ports:
-------------------

The SFP port control lines are hardwired, except for tx-disable. These
lines are controller by the RTL8231 in shift register mode. There is
no driver support for this yet.

However, to enable the lasers on SFP1 and SFP2 respectively:

    echo 0x0510ff00 > /sys/kernel/debug/rtl838x/led/led_p_en_ctrl
    echo      0x140 > /sys/kernel/debug/rtl838x/led/led_sw_p_ctrl.26
    echo      0x140 > /sys/kernel/debug/rtl838x/led/led_sw_p_ctrl.24

Install via serial console/tftp:
--------------------------------

The footprints R27 (0201) and R28 (0402) are not populated. To enable
serial console, 50 ohm resistors should be soldered -- any value from
0 ohm to 50 ohm will work. R27 can be replaced by a solder bridge.

The u-boot firmware drops to a TP-Link specific "BOOTUTIL" shell at
38400 baud. There is no known way to exit out of this shell, and no
way to do anything useful.

Ideally, one would trick the bootloader into flashing the sysupgrade
image first. However, if the image exceeds 6MiB in size, it will not
work. The sysupgrade image can also be flashed. To install OpenWrt:

Prepare a tftp server with:
 1. server address: 192.168.0.146
 2. the image as: "uImage.img"

Power on device, and stop boot by pressing any key.
Once the shell is active:
 1. Ground out the CLK (pin 16) of the ROM (U7)
 2. Select option "3. Start"
 3. Bootloader notes that "The kernel has been damaged!"
 4. Release CLK as sson as bootloader thinks image is corrupted.
 5. Bootloader enters automatic recovery -- details printed on console
 6. Watch as the bootloader flashes and boots OpenWrt.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
[OpenWrt capitalisation in commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-09-13 09:22:26 +02:00
Alexandru Gagniuc
ab2a4c1e01 realtek: rtl8380-tl-sg2xxx: use a single "firmware" partition
The "firmware" partition was assembled from two contiguous partitions.
This complexity is unnecessary. Instead of using mtd-concat over
"sys" and "usrimg1", simply declare the "firmware" partition to cover
the flash space instead.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2022-09-13 09:22:26 +02:00
Alexandru Gagniuc
d55c087390 realtek: tl-sg2xxx: read MAC address from nvmem-cells
The TP-Link RTL83xx based switches have their MAC address programmed
in the "para" partition. While in theory, the format of this partition
is dynamic, in practice, the MAC address appears to be located at a
consistent address. Thus, use nvmem-cells to read this MAC address.

The main MAC is required for deriving the MAC address of the switch
ports. Instead of reading it via mtd_get_mac_binary(), alias the
ethernet0 node as the label-mac-device, and use get_mac_label().

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2022-09-13 09:22:26 +02:00
Alexandru Gagniuc
5f026f1272 realtek: rtl838x: label switch port dts nodes
Although PHY nodes are labeled, the port nodes were not. Labeling of
ports is useful for 'status = "disabled"' ports, which is supported
since commit 9a7f17e11f ("realtek: ignore disabled switch ports")

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2022-09-13 09:22:26 +02:00
Alexandru Gagniuc
bc9dcfb1ce realtek: split TP-Link SG2000 series devicetree
The TP-Link TL-SG2008, TL-SG2008P, and TL-SG2210P use the same board.
The main difference is that some footprints are not populated in the
lower-end models. To model this with minimal duplication, move the
devicetree to a common dtsi, leaving out just the board name.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
[remove port relabelling from commit message, already merged with commit
 18a2b29aa1 ("realtek: tl-sg2008p: fix labeling of lan ports")]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-09-13 09:22:26 +02:00
Andreas Böhler
5f8c86e654 realtek: add support for TP-Link SG2452P v4 aka T1600G-52PS v4
This is an RTL8393-based switch with 802.3af on all 48 ports.

Specifications:
---------------
 * SoC:       Realtek RTL8393M
 * Flash:     32 MiB SPI flash
 * RAM:       256 MiB
 * Ethernet:  48x 10/100/1000 Mbps with PoE+
 * Buttons:   1x "Reset" button, 1x "Speed" button
 * UART:      1x serial header, unpopulated
 * PoE:       12x TI TPS23861 I2C PoE controller, 384W PoE budget
 * SFP:       4 SFP ports

Works:
------
  - (48) RJ-45 ethernet ports
  - Switch functions
  - Buttons
  - All LEDs on front panel except port LEDs
  - Fan monitoring and basic control

Not yet enabled:
----------------
  - PoE - ICs are not in AUTO mode, so the kernel driver is not usable
  - Port LEDs
  - SFP cages

Install via web interface:
-------------------------

Not supported at this time.

Install via serial console/tftp:
--------------------------------

The U-Boot firmware drops to a TP-Link specific "BOOTUTIL" shell at
38400 baud. There is no known way to exit out of this shell, and no
way to do anything useful.

Ideally, one would trick the bootloader into flashing the sysupgrade
image first. However, if the image exceeds 6MiB in size, it will not
work. To install OpenWRT:

Prepare a tftp server with:
 1. server address: 192.168.0.146
 2. the image as: "uImage.img"

Power on device, and stop boot by pressing any key.
Once the shell is active:
 1. Ground out the CLK (pin 16) of the ROM (U6)
 2. Select option "3. Start"
 3. Bootloader notes that "The kernel has been damaged!"
 4. Release CLK as soon as bootloader thinks image is corrupted.
 5. Bootloader enters automatic recovery -- details printed on console
 6. Watch as the bootloader flashes and boots OpenWRT.

Blind install via tftp:
-----------------------

This method works when it's not feasible to install a serial header.

Prepare a tftp server with:
 1. server address: 192.168.0.146
 2. the image as: "uImage.img"
 3. Watch network traffic (tcpdump or wireshark works)
 4. Power on the device.
 5. Wait 1-2 seconds then ground out the CLK (pin 16) of the ROM (U6)
 6. When 192.168.0.30 makes tftp requests, release pin 16
 7. Wait 2-3 minutes for device to auto-flash and boot OpenWRT

Signed-off-by: Andreas Böhler <dev@aboehler.at>
2022-09-10 22:13:52 +02:00
Bjørn Mork
2ca5602864 realtek: fix RTL839x receive tag decoding
The previous fixup was incomplete, and the offsets for the
queue and crc_error cpu_tag bitfields were still wrong on
RTL839x.

Fixes: 545c6113c9 ("realtek: fix RTL838x receive tag decoding")
Suggested-by: Jan Hoffmann <jan@3e8.eu>
Signed-off-by: Bjørn Mork <bjorn@mork.no>
2022-09-09 22:11:55 +02:00
Bjørn Mork
545c6113c9 realtek: fix RTL838x receive tag decoding
Commit dc9cc0d3e2 ("realtek: add QoS and rate control") replaced a
16 bit reserved field in the RTL83xx packet header with the initial
cpu_tag word, shifting the real cpu_tag fields by one.  Adjusting for
this new shift was partially forgotten in the new RX tag decoders.

This caused the switch to block IGMP, effectively blocking IPv4
multicast.

The bug was partially fixed by commit 9d847244d9 ("realtek: fix
RTL839X receive tag decoding")

Fix on RTL838x too, including correct NIC_RX_REASON_SPECIAL_TRAP value.

Suggested-by: Jan Hoffmann <jan@3e8.eu>
Fixes: dc9cc0d3e2 ("realtek: add QoS and rate control")
Signed-off-by: Bjørn Mork <bjorn@mork.no>
2022-09-08 22:28:15 +02:00
Sander Vanheule
f1802b0db7 realtek: replace fix for spurious GPIO interrupts
8 and 16 bit writes to the GPIO peripheral are apparently not supported,
and only worked most of the time. This resulted in garbabe writes to the
interrupt mask registers, causing spurious unhandled interrupts, which
could lead to CPU lock-ups as these kept retriggering.

Instead of clearing these spurious interrupt when they occur, the
upstream patch will just make sure all register writes have the intended
result, so these don't happen at all.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-09-04 20:55:15 +02:00
Markus Stockhausen
78c0fb6927 realtek: Fix missing clock module CONFIG setting
Since introduction of clock driver we have a new kernel config
setting. Provide an initial value for the 930x targets.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-08-31 23:25:39 +02:00
Markus Stockhausen
6ff21c436d realtek: fix PLL register inconsistencies
Some devices have wrong/empty values in the PLL registers. Work
around that by reporting the default values.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-08-31 23:25:39 +02:00
John Audia
e0753c5d5c kernel: bump 5.10 to 5.10.139
All patches automatically rebased.

Signed-off-by: John Audia <therealgraysky@proton.me>
2022-08-31 23:25:39 +02:00
Alexandru Gagniuc
18a2b29aa1 realtek: tl-sg2008p: fix labeling of lan ports
The SG2008P has its ethernet ports in the rear, and LEDs in the front.
The ports should be labeled lan8->lan1, not lan1->lan8. To resolve
this, fix the phy mapping in the "ports" node.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2022-08-29 11:54:00 +02:00
Alexandru Gagniuc
f242f642bb realtek: tl-sg2008p: use correct i2c address for TPS23861
Address 0x30 is a "broadcast" address for the TPS23861. It should not
be used by drivers, as all TPS23861 devices on the bus are supposed to
respond. Change this to the correct address, 0x28.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2022-08-29 11:54:00 +02:00
Sander Vanheule
9a7f17e11f realtek: ignore disabled switch ports
When marking a switch port as disabled in the device tree, by using
'status = "disabled";', the switch driver fails on boot, causing a
restart:

    CPU 0 Unable to handle kernel paging request at virtual address
    00000000, epc == 802c3064, ra == 8022b4b4
        [ ... ]
    Call Trace:
    [<802c3064>] strlen+0x0/0x2c
    [<8022b4b4>] start_creating.part.0+0x78/0x194
    [<8022bd3c>] debugfs_create_dir+0x44/0x1c0
    [<80396dfc>] rtl838x_dbgfs_port_init+0x54/0x258
    [<80397508>] rtl838x_dbgfs_init+0xe0/0x56c

This is caused by the DSA subsystem (mostly) ignoring the port, while
rtl83xx_mdio_probe() still extracts some details on this disabled port
from the device tree, resulting in the usage of a NULL pointer where a
port name is expected.

By not probing ignoring disabled ports, no attempt is made to create a
debugfs directory later. The device then boots as expected without the
disabled port.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-08-29 08:32:42 +02:00
Markus Stockhausen
48f3746fe5 realtek: switch RTL838X/RTL839X DT to new clock driver
Use new DT clockdriver syntax for RTL838X/RTL839X targets. To make it work
we need to change some nodes:
- define the external oscillator speed (25MHz)
- define SRAM
- add clock controller
- Add second CPU for RTL839X
- map all devices to new clocks
- Remove dummy LXB clock
- add CPU OPP table

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-08-28 11:48:30 +02:00
Markus Stockhausen
7c18aab6e0 realtek: activate clock driver for RTL838X/RTL839X targets
Make use the new clock driver for RTL838X and RTL839x target devices. Of course
we will enable their primary consumer (cpufreq-dt) too. To be careful just set
the default governor to userspace. As we rely on SRAM activate that module too.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-08-28 11:48:30 +02:00
Markus Stockhausen
5df36d4849 realtek: enable basic config for cpufreq framework
A new clock driver makes more sense if it can be used from consumers
like cpufreq.  Before we enable the driver we must tell the config that
the RTL838X and RTL839X targets allow CPU frequency changing.

Even though these targets currently rely on the CPU's internal R4K
timer, MIPS_EXTERNAL_TIMER is selected to allow for CPU frequency change
testing. The Realtek timers, which are clocked by the Lexra bus, still
need to be supported and used in order to provide correct wall times
when reclocking the CPU.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[add paragraph about MIPS_EXTERNAL_TIMER to commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-08-28 11:45:03 +02:00
Markus Stockhausen
800d5fb3c6 realtek: add patch to enable new clock driver in kernel
Allow building the clock driver with kernel config options.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-08-28 11:31:21 +02:00
Markus Stockhausen
4850bd887c realtek: add RTL83XX clock driver
Add a new self-contained combined clock & platform driver that allows to
access the PLL hardware clocks of RTL83XX devices. Currently it provides
info about CPU, MEM and LXB clocks on RTL838X and RTL839X devices and
additionally allows to change the CPU clocks. Changing the clocks
multiple times on a DGS-1210-20 and a DGS-1210-52 already works well and
is multithreading safe on the RTL839X. Even a cpufreq initiated change
of the CPU clock works fine. Loading the driver will add some meaningful
logging.

[0.000000] rtl83xx-clk: initialized, CPU 500 MHz, MEM 300 MHz (8 Bit DDR3), LXB 200 MHz
[0.279456] rtl83xx-clk soc:clock-controller: rate setting enabled, CPU 325-600 MHz,
           MEM 300-300 MHz, LXB 200-200 MHz, OVERCLOCK AT OWN RISK

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[remove trailing whitespaces, C-style SPDX comments for ASM and headers]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-08-28 11:30:58 +02:00
Markus Stockhausen
1efaad03bb realtek: add PLL DT binding includes
Add some constants for sharing between DT and drivers.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-08-28 11:03:34 +02:00
Markus Stockhausen
396e190f0b realtek: more generic platform initialization
Platform startup still "guesses" the CPU clock speed by DT fixed values.
If possible take clock rates from a to be developed driver and align to
MIPS generic platfom initialization code. Pack old behaviour into a
fallback function. We might get rid of that some day.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-08-20 11:49:30 +02:00
Daniel Groth
8c04a5c456 realtek: d-link: add support for dgs-1210-10mp
General hardware info:
-------------------------------------------------------------------------------

D-Link DGS-1210-10MP is a switch with 8 ethernet ports and 2 SFP ports, all
ports Gbit capable. It is based on a RTL8380 SoC @ 500MHz, DRAM 128MB and
32MB flash. All ethernet ports are 802.3af/at PoE capable
with a total PoE power budget of 130W.

File info:
-------------------------------------------------------------------------------
The dgs-1210-10mp is very similar to dgs-1210-10p so I used that as a start.

rtl838x.mk:
 - Removed lua-rs232 package since it was a leftover from the old rtl83xx-poe
   package.
 - Updated the soc to 8380.
 - Specified device variant: F.
 - Installed the new realtek-poe package.

rtl8380_d-link_dgs-1210-10mp.dts:
 - Moved dgs-1210 family common parts and non PoE related ports on rtl8231
   to the new device tree dtsi files.

Serial connection:
-------------------------------------------------------------------------------
The UART for the SoC (115200 8N1) is available close to the front panel next
to the LED/key card connector via unpopulated standard 0.1" pin header
marked j4. Pin1 is marked with arrow and square.

Pin 1: Vcc 3,3V
Pin 2: Tx
Pin 3: Rx
Pin 4: Gnd

Installation with TFTP from u-boot
-------------------------------------------------------------------------------
I originally used the install procedure:
'OpenWrt installation using the TFTP method and serial console access' found
in the device wiki for the dgs-1210-16.
< https://openwrt.org/toh/d-link/dgs-1210-16_g1#openwrt_installation_using
_the_tftp_method_and_serial_console_access >

About the realtek-poe package
-------------------------------------------------------------------------------
The realtek-poe package is installed but there isn't any automatic PoE config
setting at this time so for now the PoE config must be edited manually.

Original OEM hardware/firmware data at first installation
-------------------------------------------------------------------------------
It has been installed, developed, and tested on a device with these OEM
hardware and firmware versions.

- U-boot: 2011.12.(2.1.5.67086)-Candidate1 (Jun 22 2020 - 15:03:58)
- Boot version: 1.01.001
- Firmware version: 6.20.007
- Hardware version: F1

Things to be done when support are developed
-------------------------------------------------------------------------------
 - realtek-poe has been included in OpenWrt but the automatic config handling
   has not been solved yet so in the future there will probably be some minor
   updates for this device to handle the poe config.
 - LED link_act and poe are per function supposed to be connected to the PoE
   system.
   But some software development is also needed to make this LED work and
   shift the LED array between act and poe indication and to shift the mode
   lights with mode key.
 - LED poe_max should probably be used as straight forward error output from
   the realtek-poe package error handling. But no code has been written for
   this.
 - SFP is currently not hot pluggable. Development is under progress to get
   working I2C communication with SFP and have them hot pluggable.
   When any device in the dgs-1210 family gets this working, I expect it
   should be possible to implement the same solution in this device.

Signed-off-by: Daniel Groth <flygarn12@gmail.com>
[Capitalisation of abbreviations, DEVICE_VARIANT and update filenames,
device compatibles on single line]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-08-20 09:02:44 +02:00
Daniel Groth
51ec9b3864 realtek: d-link: dgs-1210 remake of the device tree
I have collected the known information from the dts files we have.
After that I made a new device tree that should work for this whole D-Link
switch family.
This device tree is based on modules where you first select which SoC group
the device belongs to. Then you include the GPIO dtsi file depending on what
hardware your device has, see examples below.
This tree is also expandable for more hardware,
see the part 'Future expansion possibilities' further down.

-------------------------------------------------------------------------------
The device tree now looks like this:
                            ----------------
                            | rtl838x.dtsi |    // Note 1.
                            ----------------
                                    |
                                    |
                    ---------------------------------------
                    | rtl838x_d-link_dgs-1210_common.dtsi | // Note 2.
                    ---------------------------------------
                                |
                                |       --------------
                                |-------| device.dts |      // Note 3.
                                |       --------------
                                |
                -------------------------------------
                | rtl83xx_d-link_dgs-1210_gpio.dtsi |       // Note 4.
                -------------------------------------
                                |
                                |       --------------
                                |-------| device.dts |      // Note 5.
                                        --------------

Note 1; Included in rtl838x_d-link_dgs-1210_common.dtsi.

Note 2; SoC level information and memory mapping. Choose which one to include
		in the device dts.

Note 3; At this point dgs-1210-16 will come out here.

Note 4; In this dtsi only common board hardware based on the rtl8231 is found.
	No PoE based hardware in this dtsi.
	In this dtsi there is no <#include> to above *_common.dtsi.

Note 5; Device dts with only rtl8231 based hardware without PoE will come out
		here.

-------------------------------------------------------------------------------
How to set up in dts file:

The device dts will have one of these two <#include> alternatives.

This alternative includes only common features:
<#include "rtl838x_d-link_dgs-1210_common.dtsi">

This alternative includes common and the rtl8231 GPIO (no PoE) features:

<#include "rtl838x_d-link_dgs-1210_common.dtsi">
<#include "rtl83xx_d-link_dgs-1210_gpio.dtsi">

-------------------------------------------------------------------------------
Implementation:

Finally, I also implemented this new family device tree on the current
supported devices:
dgs-1210-10p
dgs-1210-16
dgs-1210-20
dgs-1210-28

The implementation for the dgs-1210-10p is different. I have removed the
information from the rtl8382_d-link_dgs-1210-10p.dts that is already present
in rtl838x_d-link_dgs-1210_common.dtsi.
Since the rest isn't officially probed in the device dts I do not want to
include the rtl83xx_d-link_dgs-1210_gpio.dtsi with dgs-1210-10p.dts.

Since I don't have these devices to test on I have built the original firmware
for each one of these devices before this change and saved the dtb file and
then compared the original dtb file with the dtb file built with this new
device tree.

-------------------------------------------------------------------------------
Future expansion possibilities:

In parallel with the rtl838x_d-link_dgs-1210_common.dtsi in the tree map
we can make a rtl839x_d-link_dgs-1210_common.dtsi to use the rtl839x.dtsi if
the need arises with more devices based on rtl839x soc.

When we have more PoE devices so the hardware map for these gets more clear
we can make a rtl83xx_d-link_dgs-1210_poe.dtsi below
the rtl83xx_d-link_dgs-1210_gpio.dtsi in the tree map.

I looked at the port and switch setup to see if it could be moved to the dtsi.
I decided not to touch this part now. The reason was that there isn't really
any meaningful way this could be shared between the devices.
The only thing in common over the family is the 8+2sfp ports on the
dgs-1210-10xx device.
And then there is the hot plug SFP and I2C ports that aren’t implemented
on any device. So maybe when we see the whole port map for the family
then maybe the ports can be moved to a *_common.dtsi but I don't think it is
the right moment for that now.

Signed-off-by: Daniel Groth <flygarn12@gmail.com>
[Capitalisation of abbreviations and 'D-Link']
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-08-20 09:02:44 +02:00
Alexandru Gagniuc
6d5873a162 realtek: add support for TP-Link SG2008P
Add support for the TP-Link SG2008P switch. This is an RTL8380 based
switch with 802.3af one the first four ports.

Specifications:
---------------
 * SoC:       Realtek RTL8380M
 * Flash:     32 MiB SPI flash (Vendor varies)
 * RAM:       256 MiB (Vendor varies)
 * Ethernet:  8x 10/100/1000 Mbps with PoE on 4 ports
 * Buttons:   1x "Reset" button on front panel
 * Power:     53.5V DC barrel jack
 * UART:      1x serial header, unpopulated
 * PoE:       1x TI TPS23861 I2C PoE controller

Works:
------
  - (8) RJ-45 ethernet ports
  - Switch functions
  - System LED

Not yet enabled:
----------------
  - Power-over-Ethernet (driver works, but doesn't enable "auto" mode)
  - PoE, Link/Act, PoE max and System LEDs

Install via web interface:
-------------------------

Not supported at this time.

Install via serial console/tftp:
--------------------------------

The footprints R27 (0201) and R28 (0402) are not populated. To enable
serial console, 50 ohm resistors should be soldered -- any value from
0 ohm to 50 ohm will work. R27 can be replaced by a solder bridge.

The u-boot firmware drops to a TP-Link specific "BOOTUTIL" shell at
38400 baud. There is no known way to exit out of this shell, and no
way to do anything useful.

Ideally, one would trick the bootloader into flashing the sysupgrade
image first. However, if the image exceeds 6MiB in size, it will not
work. The sysupgrade image can also be flashed. To install OpenWRT:

Prepare a tftp server with:
 1. server address: 192.168.0.146
 2. the image as: "uImage.img"

Power on device, and stop boot by pressing any key.
Once the shell is active:
 1. Ground out the CLK (pin 16) of the ROM (U7)
 2. Select option "3. Start"
 3. Bootloader notes that "The kernel has been damaged!"
 4. Release CLK as sson as bootloader thinks image is corrupted.
 5. Bootloader enters automatic recovery -- details printed on console
 6. Watch as the bootloader flashes and boots OpenWRT.

Blind install via tftp:
-----------------------

This method works when it's not feasible to install a serial header.

Prepare a tftp server with:
 1. server address: 192.168.0.146
 2. the image as: "uImage.img"
 3. Watch network traffic (tcpdump or wireshark works)
 4. Power on the device.
 5. Wait 1-2 seconds then ground out the CLK (pin 16) of the ROM (U7)
 6. When 192.168.0.30 makes tftp requests, release pin 16
 7. Wait 2-3 minutes for device to auto-flash and boot OpenWRT

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2022-08-13 19:59:47 +02:00
Alexandru Gagniuc
7bba7ccde9 realtek: EnGenius EWS2910P: use the mtd3 partition for root overlay
The root overlay is mounted on the "rootfs_data" partition. This comes
at the end of the firmware image, courtesy of mtdsplit. There is very
little space left (About 1MB), which can fill up rapidly.

The "firmware" and "firmware2" partitions are part of the bootloader
dual firmware logic. They should contain independent, valid uImages.
This leaves "jffs2-cfg" (mtd3) and "jffs2-log" (mtd4) as candidates.

mtd3 is about 13.7 MB and is used by the vendor firmware to store
configuration settings. It is only erased by vendor firmware during a
factory reset. By naming this partition "rootfs_data", it becomes the
root overlay, providing significantly more room. Even with mtdsplit
wanting to create a "rootfs_data" on the firmware partition, mtd3 is
used as the overlay.

Rename "jffs2-cfg" to "rootfs_data", and profit from the extra space.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2022-08-13 19:19:38 +02:00
Sander Vanheule
225137608c realtek: Netgear GS110TPP v1: add lan9 and lan10
The original commit for the GS110TP was missing ports 9 and 10. These
are provided by an external RTL8214C phy, for which no support was
available at the time. Now that this phy is supported, add the missing
entries to enable all device ports.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-08-13 19:15:46 +02:00
Paul Spooren
ead7e5b4c3 realtek: skip SFP ports in PoE setup
The function `ucidef_set_poe` receives a list of ports to add to the PoE array.
Since switches have many ports the varibale `lan_list` is passed instead of
writing every single lan port. However, this list includes partly SFP ports
which are unrelated to PoE.

This commits adds the option to add a third parameter to manually exclide
interfaces, usually the last two.

Signed-off-by: Paul Spooren <mail@aparcar.org>
[Replace glob by regex to be more specific about matching characters]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-08-13 19:15:46 +02:00
Hauke Mehrtens
ff06edd1f0 kernel: Activate CONFIG_GPIOLIB in generic configuration
All targets expect the malta target already activate the CONFIG_GPIOLIB
option. Move it to generic kernel configuration and also activate it for
malta.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2022-08-10 21:36:17 +02:00
INAGAKI Hiroshi
cef3f05a55 realtek: add support for Panasonic Switch-M48eG PN28480K
Panasonic Switch-M48eG PN28480K is a 48 + 4 port gigabit switch, based on
RTL8393M.

Specification:

- SoC           : Realtek RTL8393M
- RAM           : DDR3 128 MiB (Winbond W631GG8KB-15)
- Flash         : SPI-NOR 32 MiB (Macronix MX25L25635FMI-10G)
- Ethernet      : 10/100/1000 Mbps x48 + 2
  - port  1-40  : TP, RTL8218B x5
  - port 41-48  : RTL8218FB
    - port 41-44: TP
    - port 45-48: TP/SFP (Combo)
- LEDs/Keys     : 7x / 1x
- UART          : RS-232 port on the front panel (connector: RJ-45)
  - 3:TX, 4:GND, 5:GND, 6:RX (pin number: RJ-45)
  - 9600n8
- Power         : 100-240 VAC, 50/60 Hz, 0.5 A
  - Plug        : IEC 60320-C13
- Stock OS      : VxWorks based

Flash instruction using initramfs image:

1.  Prepare the TFTP server with the IP address 192.168.1.111
2.  Rename the OpenWrt initramfs image to "0101A8C0.img" and place it to
    the TFTP directory
3.  Download the official upgrading firmware (ex: pn28480k_v30000.rom)
    and place it to the TFTP directory
4.  Boot M48eG and interrupt the U-Boot with Ctrl + C keys
5.  Execute the following commands and boot with the OpenWrt initramfs
    image

    rtk network on
    tftpboot 0x81000000
    bootm

6.  Backup mtdblock files to the computer by scp or anything and reboot
7.  Interrupt the U-Boot and execute the following commands to re-create
    filesystem in the flash

    ffsmount c:/
    ffsfmt c:/

    this step takes a long time, about ~ 4 mins

8.  Execute the following commands to put the official images to the
    filesystem

    updatert <official image>

    example:

      updatert pn28480k_v30000.rom

    this step takes about ~ 40 secs

9.  Set the environment variables of the U-Boot by the following commands

    setenv loadaddr 0xb4e00000
    setenv bootcmd 'sleep 10; bootm;'
    saveenv

    'sleep 10;' is required as dummy to execute 'bootm' command correctly

10: Download the OpenWrt initramfs image and boot with it

    tftpboot 0x81000000 0101A8C0.img
    bootm

11: On the initramfs image, download the sysupgrade image and perform
    sysupgrade with it

    sysupgrade <imagename>

12: Wait ~ 120 seconds to complete flashing

Known Issues:

- 4x SFP ports are provided as combo ports by the RTL8218FB chip, but the
  phy driver has no support for it. Currently, only TP ports work by the
  RTL8218B support.

Note:

- "Switch-M48eG" is a model name, and "PN28480K" is a model number.
  Switch-M48eG has an another (old) model number ("PN28480"), it's not a
  Realtek based hardware.

- Switch-M48eG has a "POWER" LED (Green), but it's not connected to any
  GPIO pin.

- U-Boot checks the runtime images in the flash when booting and fails
  to execute "bootcmd" variable if the images are not existing.

- A filesystem is formed in the flash (0x100000-0x1DFFFFF) on the stock
  firmware and it includes the stock images, configuration files and
  checksum files. It's unknown format, can't be managed on the OpenWrt.
  To get the enough space for OpenWrt, move the filesystem to the head
  of "fs_reserved" partition by execution of "ffsfmt" and "updatert".

- A GPIO pin on PCA9539 is used for resetting external RTL8218B phys and
  RTL8218FB phy.
  This should be specified as "reset-gpios" property in MDIO node, but
  the current configuration of RTL8218B phy in the driver seems to be
  incomplete and RTL8218FB won't be configured on RTL8218D support.
  So, ethernet ports on these phys will be broken after hard-resetting.
  At the moment, configure this pin as gpio-hog to avoid breaking by
  resetting.

- This model has 2x Microchip TCN75A thermal sensors. Linux Kernel
  supports TCN75 chip on lm75 driver, but no support for TCN75'A'
  variant.
  At the moment, use TCN75 support for the chips instead.

Back to the stock firmware:

1. Delete "loadaddr" variable and set "bootcmd" to the original value

   on U-Boot:

     setenv loadaddr
     setenv bootcmd 'ffsrdm c:/runtime.had 0x81000000;alphadec c:/runtime.had 0x81000240 0x80010000;'

   on OpenWrt:

     fw_setenv loadaddr
     fw_setenv bootcmd 'ffsrdm c:/runtime.had 0x81000000;alphadec c:/runtime.had 0x81000240 0x80010000;'

2. Perform reset or reboot

  on U-Boot:

    reset

  on OpenWrt:

    reboot

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2022-08-06 14:39:57 +02:00
INAGAKI Hiroshi
4974ee7341 realtek: enable pca953x GPIO driver for rtl839x subtarget
The system status LED on Panasonic Switch-M48eG PN28480K is connected to
a PCA9539PW. To use the LED as a status LED of OpenWrt while booting,
enable the pca953x driver and built-in to the kernel.
Also enable CONFIG_GPIO_PCA953X_IRQ to use interrupt via RTL83xx GPIO.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2022-08-06 14:39:57 +02:00
INAGAKI Hiroshi
fa52e5e254 realtek: add support for Panasonic Switch-M24eG PN28240K
Panasonic Switch-M24eG PN28240K is a 24 + 2 port gigabit switch, based on
RTL8382M.

Specification:

- SoC           : Realtek RTL8382M
- RAM           : DDR3 128 MiB (Winbond W631GG8KB-15)
- Flash         : SPI-NOR 32 MiB (Macronix MX25L25635FMI-10G)
- Ethernet      : 10/100/1000 Mbps x24 + 2
  - port  1-8   : TP, RTL8218B
  - port  9-16  : TP, RTL8218B (SoC)
  - port 17-24  : RTL8218FB
    - port 17-22: TP
    - port 23-24: TP/SFP (Combo)
- LEDs/Keys     : 7x / 1x
- UART          : RS-232 port on the front panel (connector: RJ-45)
  - 3:TX, 4:GND, 5:GND, 6:RX (pin number: RJ-45)
  - 9600n8
- Power         : 100-240 VAC, 50/60 Hz, 0.5 A
  - Plug        : IEC 60320-C13
- Stock OS      : VxWorks based

Flash instruction using initramfs image:

1.  Prepare the TFTP server with the IP address 192.168.1.111
2.  Rename the OpenWrt initramfs image to "0101A8C0.img" and place it to
    the TFTP directory
3.  Download the official upgrading firmware (ex: pn28240k_v30000.rom)
    and place it to the TFTP directory
4.  Boot M24eG and interrupt the U-Boot with Ctrl + C keys
5.  Execute the following commands and boot with the OpenWrt initramfs
    image

    rtk network on
    tftpboot 0x81000000
    bootm

6.  Backup mtdblock files to the computer by scp or anything and reboot
7.  Interrupt the U-Boot and execute the following commands to re-create
    filesystem in the flash

    ffsmount c:/
    ffsfmt c:/

    this step takes a long time, about ~ 4 mins

8.  Execute the following commands to put the official images to the
    filesystem

    updatert <official image>

    example:

      updatert pn28240k_v30000.rom

    this step takes about ~ 40 secs

9.  Set the environment variables of the U-Boot by the following commands

    setenv loadaddr 0xb4e00000
    setenv bootcmd bootm
    saveenv

10: Download the OpenWrt initramfs image and boot with it

    tftpboot 0x81000000 0101A8C0.img
    bootm

11: On the initramfs image, download the sysupgrade image and perform
    sysupgrade with it

    sysupgrade <imagename>

12: Wait ~ 120 seconds to complete flashing

Known Issues:

- 2x SFP ports are provided as combo ports by the RTL8218FB chip, but the
  phy driver has no support for it. Currently, only TP ports work by the
  RTL8218D support.

Note:

- "Switch-M24eG" is a model name, and "PN28240K" is a model number.
  Switch-M24eG has an another (old) model number ("PN28240"), it's not a
  Realtek based hardware.

- Switch-M24eG has a "POWER" LED (Green), but it's not connected to any
  GPIO pin.

- U-Boot checks the runtime images in the flash when booting and fails
  to execute "bootcmd" variable if the images are not existing.

- A filesystem is formed in the flash (0x100000-0x1DFFFFF) on the stock
  firmware and it includes the stock images, configuration files and
  checksum files. It's unknown format, can't be managed on the OpenWrt.
  To get the enough space for OpenWrt, move the filesystem to the head
  of "fs_reserved" partition by execution of "ffsfmt" and "updatert".

- A GPIO pin on PCA9539 is used for resetting external RTL8218B phy and
  RTL8218FB phy.
  This should be specified as "reset-gpios" property in MDIO node, but
  the current configuration of RTL8218B phy in the phy driver seems to
  be incomplete and RTL8218FB won't be configured on RTL8218D support.
  So, ethernet ports on these phys will be broken after hard-resetting.
  At the moment, configure this pin as gpio-hog to avoid breaking by
  resetting.

Back to the stock firmware:

1. Delete "loadaddr" variable and set "bootcmd" to the original value

   on U-Boot:

     setenv loadaddr
     setenv bootcmd 'bootm 0x81000000'

   on OpenWrt:

     fw_setenv loadaddr
     fw_setenv bootcmd 'bootm 0x81000000'

2. Perform reset or reboot

  on U-Boot:

    reset

  on OpenWrt:

    reboot

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2022-08-06 14:39:57 +02:00
INAGAKI Hiroshi
3d669ec9cd realtek: add support for Panasonic Switch-M16eG PN28160K
Panasonic Switch-M16eG PN28160K is a 16 + 2 port gigabit switch, based on
RTL8382M.

Specification:

- SoC           : Realtek RTL8382M
- RAM           : DDR3 128 MiB (Winbond W631GG8KB-15)
- Flash         : SPI-NOR 32 MiB (Macronix MX25L25635FMI-10G)
- Ethernet      : 10/100/1000 Mbps x16 + 2
  - port 1-8    : TP, RTL8218B (SoC)
  - port 9-16   : RTL8218FB
    - port  9-14: TP
    - port 15-16: TP/SFP (Combo)
- LEDs/Keys     : 7x / 1x
- UART          : RS-232 port on the front panel (connector: RJ-45)
  - 3:TX, 4:GND, 5:GND, 6:RX (pin number: RJ-45)
  - 9600n8
- Power         : 100-240 VAC, 50/60 Hz, 0.5 A
  - Plug        : IEC 60320-C13
- Stock OS      : VxWorks based

Flash instruction using initramfs image:

1.  Prepare the TFTP server with the IP address 192.168.1.111
2.  Rename the OpenWrt initramfs image to "0101A8C0.img" and place it to
    the TFTP directory
3.  Download the official upgrading firmware (ex: pn28160k_v30003.rom)
    and place it to the TFTP directory
4.  Boot M16eG and interrupt the U-Boot with Ctrl + C keys
5.  Execute the following commands and boot with the OpenWrt initramfs
    image

    rtk network on
    tftpboot 0x81000000
    bootm

6.  Backup mtdblock files to the computer by scp or anything and reboot
7.  Interrupt the U-Boot and execute the following commands to re-create
    filesystem in the flash

    ffsmount c:/
    ffsfmt c:/

    this step takes a long time, about ~ 4 mins

8.  Execute the following commands to put the official images to the
    filesystem

    updatert <official image>

    example:

      updatert pn28160k_v30003.rom

    this step takes about ~ 40 secs

9.  Set the environment variables of the U-Boot by the following commands

    setenv loadaddr 0xb4e00000
    setenv bootcmd bootm
    saveenv

10: Download the OpenWrt initramfs image and boot with it

    tftpboot 0x81000000 0101A8C0.img
    bootm

11: On the initramfs image, download the sysupgrade image and perform
    sysupgrade with it

    sysupgrade <imagename>

12: Wait ~ 120 seconds to complete flashing

Known Issues:

- 2x SFP ports are provided as combo ports by the RTL8218FB chip, but the
  phy driver has no support for it. Currently, only TP ports work by the
  RTL8218D support.

Note:

- "Switch-M16eG" is a model name, and "PN28160K" is a model number.
  Switch-M16eG has an another (old) model number ("PN28160"), it's not a
  Realtek based hardware.

- Switch-M16eG has a "POWER" LED (Green), but it's not connected to any
  GPIO pin.

- U-Boot checks the runtime images in the flash when booting and fails
  to execute "bootcmd" variable if the images are not existing.

- A filesystem is formed in the flash (0x100000-0x1DFFFFF) on the stock
  firmware and it includes the stock images, configuration files and
  checksum files. It's unknown format, can't be managed on the OpenWrt.
  To get the enough space for OpenWrt, move the filesystem to the head
  of "fs_reserved" partition by execution of "ffsfmt" and "updatert".

- A GPIO pin on PCA9539 is used for resetting external RTL8218FB phy.
  This should be specified as "reset-gpios" property in MDIO node, but
  RTL8218FB won't be configured on RTL8218D support in the phy driver.
  So, ethernet ports on the phy will be broken after hard-resetting.
  At the moment, configure this pin as gpio-hog to avoid breaking by
  resetting.

Back to the stock firmware:

1. Delete "loadaddr" variable and set "bootcmd" to the original value

   on U-Boot:

     setenv loadaddr
     setenv bootcmd 'bootm 0x81000000'

   on OpenWrt:

     fw_setenv loadaddr
     fw_setenv bootcmd 'bootm 0x81000000'

2. Perform reset or reboot

  on U-Boot:

    reset

  on OpenWrt:

    reboot

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2022-08-06 14:39:57 +02:00
Olliver Schinagl
943905b0b6 realtek: Fix typo in Kconfig prompt
As the symbol RTL930x shows, the bool enables the RTL930x platform, not
the RTL839x one.

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
(slightly changed commit subject)
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
2022-08-05 14:10:42 +02:00
Daniel Golle
a49212d762 Revert "realtek: remove support for HPE 1920 series"
This reverts commit a63aeaecf1.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
2022-07-28 16:45:19 +02:00
Sander Vanheule
a63aeaecf1 realtek: remove support for HPE 1920 series
Support for HPE 1920 images depends on two non-existent tools (mkh3cimg
and mkh3cvfs) from the in the firmware-utils package. Revert commit
f2f09bc002 ("realtek: add support for HPE 1920 series") until support
for these tools is merged and made available in OpenWrt.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-07-28 15:17:04 +02:00
Jan Hoffmann
f2f09bc002 realtek: add support for HPE 1920 series
Hardware information:
---------------------

- HPE 1920-8G:
  - RTL8380 SoC
  - 8 Gigabit RJ45 ports (built-in RTL8218B)
  - 2 SFP ports (built-in SerDes)

- HPE 1920-16G / HPE 1920-24G (same board):
  - RTL8382 SoC
  - 16/24 Gigabit RJ45 ports (built-in RTL8218B, 1/2 external RTL8218D)
  - 4 SFP ports (external RTL8214FC)

- Common:
  - RJ45 RS232 port on front panel
  - 32 MiB NOR Flash
  - 128 MiB DDR3 DRAM
  - PT7A7514 watchdog

Booting initramfs image:
------------------------

- Prepare a FTP or TFTP server serving the OpenWrt initramfs image and
  connect the server to a switch port.

- Connect to the console port of the device and enter the extended
  boot menu by typing Ctrl+B when prompted.

- Choose the menu option "<3> Enter Ethernet SubMenu".

- Set network parameters via the option "<5> Modify Ethernet Parameter".
  Enter the FTP/TFTP filename as "Load File Name" ("Target File Name"
  can be left blank, it is not required for booting from RAM). Note that
  the configuration is saved on flash, so it only needs to be done once.

- Select "<1> Download Application Program To SDRAM And Run".

Initial installation:
---------------------

- Boot an initramfs image as described above, then use sysupgrade to
  install OpenWrt permanently. After initial installation, the
  bootloader needs to be configured to load the correct image file

- Enter the extended boot menu again and choose "<4> File Control",
  then select "<2> Set Application File type".

- Enter the number of the file "openwrt-kernel.bin" (should be 1), and
  use the option "<1> +Main" to select it as boot image.

- Choose "<0> Exit To Main Menu" and then "<1> Boot System".

NOTE: The bootloader on these devices can only boot from the VFS
filesystem which normally spans most of the flash. With OpenWrt, only
the first part of the firmware partition contains a valid filesystem,
the rest is used for rootfs. As the bootloader does not know about this,
you must not do any file operations in the bootloader, as this may
corrupt the OpenWrt installation (selecting the boot image is an
exception, as it only stores a flag in the bootloader data, but doesn't
write to the filesystem).

Signed-off-by: Jan Hoffmann <jan@3e8.eu>
2022-07-28 14:08:56 +02:00
Jan Hoffmann
81e3017609 realtek: clean up rtl838x MDIO busy wait loop
Don't use udelay to allow other kernel tasks to execute if the kernel
has been built without preemption. Also determine the timeout based on
jiffies instead of loop iterations.

This is especially important on devices containing a watchdog with a
short timeout. Without this change, the watchdog is not serviced during
PHY patching which can take multiple seconds.

Tested-by: Birger Koblitz <mail@birger-koblitz.de>
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
2022-07-28 14:08:51 +02:00
Jan Hoffmann
b6a0d50b7f realtek: add SFP support for RTL8214FC PHY
Probe the SFP module during PHY initialization and implement
insertion/removal handlers to automatically configure the media type
of the respective port.

Suggested-by: Birger Koblitz <git@birger-koblitz.de>
Tested-by: Birger Koblitz <mail@birger-koblitz.de>
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
2022-07-28 14:08:43 +02:00
Jan Hoffmann
c6a7ea9f7f realtek: rtl83xx-phy: decouple RTL8214FC media change and power config
Move RTL8214FC power configuration to newly created suspend and resume
methods. A media change now only results in power configuration if the
PHY is not suspended, to avoid powering up a port when the interface is
currently not up.

While at it, remove the rtl8380 prefix from function names, as this is
actually not SoC-specific.

Tested-by: Birger Koblitz <mail@birger-koblitz.de>
Signed-off-by: Jan Hoffmann <jan@3e8.eu>
2022-07-28 14:08:07 +02:00
Jan Hoffmann
bac50e39a7 realtek: rtl83xx-phy: fix RTL8214FC media change
Toggle power on the individual PHY instead of the package. Otherwise
a media change always toggles power on the first port, and not the one
that is being configured.

Signed-off-by: Jan Hoffmann <jan@3e8.eu>
2022-07-28 14:07:10 +02:00
Markus Stockhausen
b2681e584c realtek: make DGS-1210 u-boot-env partition writeable
We are close to provide enduser friendly OpenWrt images for DGS-1210
switches that do not need serial console. Nevertheless a small bit is
missing. We cannot switch back to the vendor partition or initiate a
download of a vendor firmware image. To issue this from inside OpenWrt
we need write access to U-Boot environment.

Case 1: Switch back to secondary (vendor) image
> fw_setenv bootcmd run addargs\; bootm 0xb4e80000
> fw_setenv image /dev/mtdblock7
> reboot

Case 2: Issue D-Link Network Assistant based download on next reboot.
This is a combination of some vendor specific protocol (DDP) and a
TFTP download afterwards.
> fw_setenv bootstop on
> reboot

Allow these commands by opening up u-boot-env for write access.
Tested on DGS-1210-20.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-07-26 09:15:38 +02:00
Sander Vanheule
a3e4949998 realtek: clear spurious GPIO interrupts
The interrupt controller in the internal GPIO peripheral will sometimes
generate spurious interrupts. If these are not properly acknowledged, the
system will be held busy until reboot. These spurious interrupts are identified
by the fact that there is no system IRQ number associated, since the interrupt
line was never allocated. Although most prevalent on RTL839x, RTL838x SoCs have
also displayed this behaviour.

Reported-by: Luiz Angelo Daros de Luca <luizluca@gmail.com> # DGS-1210-52
Reported-by: Birger Koblitz <mail@birger-koblitz.de> # Netgear GS724TP v2
Reported-by: Jan Hoffmann <jan@3e8.eu> # HPE 1920-16G
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-07-21 22:44:01 +02:00
Sander Vanheule
1773264a0c realtek: correct egress frame port verification
Destination switch ports for outgoing frame can range from 0 to
CPU_PORT-1.

Refactor the code to only generate egress frame CPU headers when a valid
destination port number is available, and make the code a bit more
consistent between different switch generations. Change the dest_port
argument's type to 'unsigned int', since only positive values are valid.

This fixes the issue where egress frames on switch port 0 did not
receive a VLAN tag, because they are sent out without a CPU header.
Also fixes a potential issue with invalid (negative) egress port numbers
on RTL93xx switches.

Reported-by: Arınç ÜNAL <arinc.unal@xeront.com>
Suggested-by: Birger Koblitz <mail@birger-koblitz.de>
Tested-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-07-17 10:06:51 +02:00
Sander Vanheule
0b35a08a05 realtek: correct egress frame priority assignment
Priority values passed to the egress (TX) frame header initialiser are
invalid when smaller than 0, and should not be assigned to the frame.
Queue assignment is then left to the switch core logic.

Current code for RTL83xx forces the passed priority value to be
positive, by always masking it to the lower bits, resulting in the
priority always being set and enabled. RTL93xx code doesn't even check
the value and unconditionally assigns the (32 bit) value to the (5 bit)
QID field without masking.

Fix priority assignment by only setting the AS_QID/AS_PRI flag when a
valid value is passed, and properly mask the value to not overflow the
QID/PRI field.

For RTL839x, also assign the priority to the right part of the frame
header. Counting from the leftmost bit, AS_PRI and PRI are in bits 36
and 37-39. The means they should be assigned to the third 16 bit value,
containing bits 32-47.

Tested-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-07-17 10:06:46 +02:00
Sander Vanheule
d6165ea75b realtek: fix egress L2 learning on rtl839x
The flag to enable L2 address learning on egress frames is in CPU header
bit 40, with bit 0 being the leftmost bit of the header. This
corresponds to BIT(7) in the third 16-bit value of the header.

Correctly set L2LEARNING by fixing the off-by-one error.

Fixes: 9eab76c84e ("realtek: Improve TX CPU-Tag usage")
Tested-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-07-17 10:06:40 +02:00
Sander Vanheule
d9516cacb0 realtek: fix egress port mask on rtl839x
The flag to enable the outgoing port mask is in CPU header bit 43, with
bit 0 being the leftmost bit of the header. This corresponds to BIT(4)
in the third 16-bit value of the header.

Correctly set AS_DPM by fixing the off-by-one error.

Fixes: 9eab76c84e ("realtek: Improve TX CPU-Tag usage")
Tested-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-07-17 10:06:32 +02:00
Sander Vanheule
eae5e55a79 realtek: remove hardcoded sys-led configurations
setup.c unconditionally sets the sys-led mode (blinking rate) to a
permanent high output. This may cause issues when a board expects this
pin to toggle periodically, e.g. when hooked up to an external watchdog.

If the sys-led peripheral is used to control an LED, the mux should be
configured to use the pin as GPIO0, allowing for better control as a
GPIO LED.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-07-10 09:54:35 +02:00
Sander Vanheule
b03109c094 realtek: add mux pinctrl for rtl931x
Add a pinctrl-single node to manage the sys-led mux and JTAG mux.
This allows using the associated pins as GPIOs:
  - sys-led: GPIO0
  - JTAG: GPIO6, GPIO7, others unknown (TDO, TDI, TMS, TCK /TRST)

Suggested-by: Birger Koblitz <mail@birger-koblitz.de>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-07-10 09:54:35 +02:00
Sander Vanheule
3edb5e841c realtek: add system LED for ZyXEL XGS1250-12
The devicetree for the ZyXEL XGS1250-12 was missing the description of
the front panel LED labeled "PWR SYS". Let's add it so it can be
controlled by the user.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-07-10 09:54:35 +02:00
Sander Vanheule
cd7a225d28 realtek: add sys-led disable pinctrl for rtl930x
Like for RTL838x devices, add a pinctrl-single node to manage the
sys-led/gpio0 mux, and allow using the pin as GPIO.

Co-developed-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-07-10 09:54:35 +02:00
Sander Vanheule
f4065485d3 realtek: add missing gpio0 pinctrl properties
Not all devices using the gpio0/sys-led pin as a GPIO, configure the
pinmux. Add the necessary pinctrl properties to these devices to ensure
the pin is set up for use as GPIO.

Co-developed-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Bjørn Mork <bjorn@mork.no>
2022-07-10 09:54:35 +02:00
Markus Stockhausen
fae3ac3560 realtek: build sane factory images for DGS-1210 models
During upload of firmware images the WebUI and CLI patch process
extracts a version information from the uploaded file and stores it
onto the jffs2 partition. To be precise it is written into the
flash.txt or flash2.txt files depending on the selected target image.
This data is not used anywhere else. The current OpenWrt factory
image misses this label. Therefore version information shows only
garbage. Fix this.

Before:
DGS-1210-20> show firmware information
IMAGE ONE:
Version      : xfo/QE~WQD"A\Scxq...
Size         : 5505185 Bytes

After:
DGS-1210-20> show firmware information
IMAGE ONE:
Version      : OpenWrt
Size         : 5505200 Bytes

Tested-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-07-08 20:15:22 +02:00
Markus Stockhausen
2b49ec3a28 realtek: build factory images for all DGS-1210 models
Currently we build factory images only for DGS-1210-28 model. Relax
that constraint and take care about all models. Tested on DGS-1210-20
and should work on other models too because of common flash layout.

Tested-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-07-08 20:15:22 +02:00
Luiz Angelo Daros de Luca
8b798dbb39 realtek: rename u-boot-env2 to board-name
Some realtek boards have two u-boot-env partitions. However, in the
DGS-1210 series, the mtdblock2 partition is not a valid u-boot env
and simply contains the board/device name, followed by nulls.

00000000  44 47 53 2d 31 32 31 30  2d 32 38 2d 46 31 00 00 |DGS-1210-28-F1..|
00000010  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00 |................|
*
00040000

00000000  44 47 53 2d 31 32 31 30  2d 35 32 2d 46 31 00 00 |DGS-1210-52-F1..|
00000010  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00 |................|
*
00040000

The misleading u-boot-env2 name also confuses uboot-envtools.

Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
2022-07-05 21:52:14 +02:00
Markus Stockhausen
e763c4c89f realtek: build DGS-1210 images with CAMEO tag
From now on we will insert CAMEO tags into sysupgrade images for
DGS-1210 devices. This will make the "OS:...FAILED" and "FS:...FAILED"
messages go away.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-07-05 09:56:37 +02:00
Alexandru Gagniuc
36acb3db03 realtek: EnGenius EWS2910P: declare and hog the poe-enable GPIO
GPIO 1 on the RTL8231 is used to force the PoE MCU to disable power
outputs. It is not used by any driver, but if accidentally set low,
PoE outputs are disabled. This situation is hard to debug, and
requires knowledge of the Broadcom PoE protocol used by the MCU.

To prevent this situation, hog it as an output high. This is
consistent with the ZyXel GS1900 series handles it.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2022-07-02 11:50:47 +02:00
Luiz Angelo Daros de Luca
1005dc0a64 realtek: add DGS-1210-28 factory image
DGS-1210 switches support dual image, with each image composed of a
kernel and a rootfs partition. For image1, kernel and rootfs are in
sequence. The current OpenWrt image (written using a serial console),
uses those partitions together as the firmware partition, ignoring the
partition division. The current OEM u-boot fails to validate image1 but
it will only trigger firmware recovery if both image1 and image2 fail,
and it does not switch the boot image in case one of them fails the
check.

The OEM factory image is composed of concatenated blocks of data, each
one prefixed with a 0x40-byte cameo header. A normal OEM firmware will
have two of these blocks (kernel, rootfs). The OEM firmware only checks
the header before writing unconditionally the data (except the header)
to the correspoding partition.

The OpenWrt factory image mimics the OEM image by cutting the
kernel+rootfs firmware at the exact size of the OEM kernel partition
and packing it as "the kernel partition" and the rest of the kernel and
the rootfs as "the rootfs partition". It will only work if written to
image1 because image2 has a sysinfo partition between kernel2 and
rootfs2, cutting the kernel code in the middle.

Steps to install:

1) switch to image2 (containing an OEM image), using web or these CLI
   commands:
   - config firmware image_id 2 boot_up
   - reboot
2) flash the factory_image1.bin to image1. OEM web (v6.30.016)
   is crashing for any upload (ssh keys, firmware), even applying OEM
   firmwares. These CLI commands can upload a new firmware to the other
   image location (not used to boot):
   - download firmware_fromTFTP <tftpserver> factory_image1.bin
   - config firmware image_id 1 boot_up
   - reboot

To debrick the device, you'll need serial access. If you want to
recover to an OpenWrt, you can replay the serial installation
instructions. For returning to the original firmware, press ESC during
the boot to trigger the emergency firmware recovery procedure. After
that, use D-Link Network Assistant v2.0.2.4 to flash a new firmware.

The device documentation does describe that holding RESET for 12s
trigger the firmware recovery. However, the latest shipped U-Boot
"2011.12.(2.1.5.67086)-Candidate1" from "Aug 24 2021 - 17:33:09" cannot
trigger that from a cold boot. In fact, any U-Boot procedure that relies
on the RESET button, like reset settings, will only work if started from
a running original firmware. That, in practice, cancels the benefit of
having two images and a firmware recovery procedure (if you are not
consider dual-booting OpenWrt).

Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
2022-06-28 22:20:09 +02:00
Markus Stockhausen
78b7be9f6c realtek: cleanup LAG logging
Setting up DSA bond silently fails if mode is not 802.3ad. Add log message
to fix it. As we are already here harmonize all logging messages in the
add/delete functions.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
2022-06-26 11:02:15 +02:00
Alexandru Gagniuc
4d1fc8916c realtek: EnGenius EWS2910P: add support for SFP ports
The SFP cages 9F and 10F share the same SCL line. Currently, there
isn't a good way to model this. Thus, only one SFP port can be fully
supported.

Cage 10F is fully supported with an I2C bus and sfp handle. Linux
automatically handles enabling or disabling the TX laser.

Cage 9F is only parially supported, without the sfp handle. The SDA
line is hogged as an input, so that it remains high. SCL transitions
sould not affect modules connected to this cage. The default value of
the tx-disable line is high (active). It is exported as a gpio, but
the laser is off by default. To enable the laser:

    echo 0 > /sys/class/gpio/sff-p9-tx-disable/value

Thus, both modules can be used for networking, but only 10F will be
able to detect and identify a plugged in SFP module.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2022-06-25 15:45:30 +02:00
Alexandru Gagniuc
2cfaab4549 realtek: add support for EnGenius EWS2910P
Add support for the Engenius EWS2910P PoE switch. This is an RTL8380
based switch with two SFP slots, and PoE 802.3af one every RJ-45 port.

The specs say 802.3af, but the vendor firmware configures the PSE for
a budget of 31W, indicating 802.3at support.

Specifications:
---------------
* SoC:       Realtek RTL8380M
* Flash:     32 MiB SPI flash Macronix MX25L25635E
* RAM:       256 MiB (As reported by bootloader)
* Ethernet:  16x 10/100/1000 Mbps with PoE
              2x SFP slots
* Buttons:   1 "Reset" button on front panel
             1 "LED mode: button on front panel
             1 "On/Off" Toggle switch on the back
* Power:     48V-54V DC barrel jack
* UART:      1 serial header (JP1) with populated 2.54mm pitch header
             Labeled GRTV for ground, rx, tx, and 3.3V respectively
* PoE:       1 STM ST32F100 microcontroller
             2 BCM59111 PSE chips
Works:
------
  - (8) RJ-45 ethernet ports
  - Switch functions
  - LEDs and buttons

Not yet enabled:
----------------
  - SFP ports (will be enabled in a subsequent change)
  - Power-over-Ethernet (requires realtek-poe package)

Install via web interface:
-------------------------

The factory firmware will accept and flash the initramfs image. It is
recommended to flash to "Partition 0". Flashing to "Partition 1" is
not supported at this point.

The factory web GUI will show the following warning:

 " Warning: The firmware version is v0.00.00-c0.0.00
     The firmware image you are uploading is older than the current
     firmware of the switch. The device will reset back to default
     settings. Are you sure you want to proceed?"

This is expected when flashing OpenWrt. After the initramfs image
boots, flash the -sysupgrade using either the commandline or LuCI.

Install via serial console/tftp:
--------------------------------

The u-boot firmware will not stop the boot, regardless of which key is
pressed. To access the u-boot console, ground out the CLK (pin 16) of
the ROM (U22) when u-boot is reading the linux image. If timed
correctly, the image CRC will fail, and u-boot will drop to a shell:
    > rtk network on
    > setenv ipaddr <address of tftp server>
    > tftp $(freemem) <name-of-initramfs-image.bin>
    > bootm

Then flash the -sysupgrade using either the commandline or luci.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
[gpio-led node names, OpenWrt and LuCI capitalization in commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-06-25 15:43:46 +02:00
Tomasz Maciej Nowak
539e60539a generic: enable CRYPTO_LIB_BLAKE2S[_X86|_ARM]
This is now built-in, enable so it won't propagate on target configs.

Link: https://lkml.org/lkml/2022/1/3/168
Fixes: 79e7a2552e ("kernel: bump 5.15 to 5.15.44")
Fixes: 0ca9367069 ("kernel: bump 5.10 to 5.10.119")
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
(Link to Kernel's commit taht made it built-in,
CRYPTO_LIB_BLAKE2S[_ARM|_X86] as it's selectable, 5.10 backport)
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
2022-06-24 17:10:24 +02:00
Bjørn Mork
d6eebaf995 realtek: fix gcc-12 build with -Werror=array-compare
Removing this gcc-12 error:

arch/mips/rtl838x/setup.c:64:30: error: comparison between two arrays [-Werror=array-compare]
   64 |         else if (__dtb_start != __dtb_end)

Signed-off-by: Bjørn Mork <bjorn@mork.no>
2022-06-22 18:37:40 +02:00
Andreas Böhler
d9e12c21fa realtek: make "u-boot-env" partition writable for Netgear 3xx series
The Netgear GS3xx devices do not properly initialise the port LEDs during
startup unless the boot command in U-Boot is changed. Making the U-Boot
env partition writable allows this modification to be done from within
OpenWrt by calling "fw_setenv bootcmd rtk network on\; boota".

Signed-off-by: Andreas Böhler <dev@aboehler.at>
2022-06-22 17:52:30 +02:00
Stijn Segers
9c381d3386 realtek: make Netgear GS1xx u-boot env partition writable
Make the u-boot environment partition for the NETGEAR
GS108T v3 and GS110TPP writable (they share a DTS), so
the values can be manipulated from userspace.

See https://forum.openwrt.org/t/57875/1567 for a real
world example.

Signed-off-by: Stijn Segers <foss@volatilesystems.org>
2022-06-22 17:51:02 +02:00
Pascal Ernster
adbdfc9366 realtek: add support for power LED on Netgear GS108Tv3
The Netgear GS108Tv3 is already supported by OpenWrt, but is missing LED
support. After OpenWrt installation, all LEDs are off which makes the
installation quite confusing.
This enables support for the green/amber power LED to give feedback
about the current status.

This is basically just a verbatim copy of commit c4927747d2 ("realtek:
add support for power LED on Netgear GS308Tv1").

Please note that both LEDs are wired up in an anti-parallel fashion,
which means that only one of both LEDs/colors can be switched on at the
same time. If both LEDs/colors are switched on simultanously, the LED
goes dark.

Tested-by: Pascal Ernster <git@hardfalcon.net>
Signed-off-by: Pascal Ernster <git@hardfalcon.net>
[add title to commit reference]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-06-19 10:58:40 +02:00
Markus Stockhausen
6153c530cc realtek: add support for D-Link DGS-1210-20
Hardware specification
 ----------------------

 * RTL8382M SoC, 1 MIPS 4KEc core @ 500MHz
 * 128MB DRAM
 * 32MB NOR Flash
 * 16 x 10/100/1000BASE-T ports
    - Internal PHY with 8 ports (RTL8218B)
    - External PHY with 8 ports (RTL8218B)
 * 4 x Gigabit RJ45/SFP Combo ports
    - External PHY with 4 SFP ports (RTL8214FC)
 * Power LED
 * Reset button on front panel
 * UART (115200 8N1) via unpopulated standard 0.1" pin header marked J6

 UART pinout
 -----------

  [o]ooo|J6
   | ||`------ GND
   | |`------- RX
   | `-------- TX
   `---------- Vcc (3V3)

 Boot initramfs image from U-Boot
 --------------------------------

  1. Press Escape key during `Hit Esc key to stop autoboot` prompt
  2. Press CTRL+C keys to get into real U-Boot prompt
  3. Init network with `rtk network on` command
  4. Load image with `tftpboot 0x8f000000 openwrt-realtek-rtl838x-d-link_dgs-1210-20-initramfs-kernel.bin` command
  5. Boot the image with `bootm` command

To install, upload the sysupgrade image to the OEM webpage or sysupgrade
from the system running from initramfs image.

It has been developed and tested on device with F1 revision.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[correct initramfs image name]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-06-19 08:36:21 +02:00
Andreas Böhler
c4927747d2 realtek: add support for power LED on Netgear GS308Tv1
The Netgear GS308Tv1 is already supported by OpenWrt, but is missing LED
support. After OpenWrt installation, all LEDs are off which makes the
installation quite confusing.
This enables support for the green/amber power LED to give feedback
about the current status.

Signed-off-by: Andreas Böhler <dev@aboehler.at>
2022-06-18 09:21:50 +02:00
Luiz Angelo Daros de Luca
f5a87a0a7b realtek: add gpio-restart for D-Link DGS-1210-28
A GPIO assert is required to reset the system. Otherwise, the system
will hang on reboot.

Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Reviewed-by: Robert Marko <robimarko@gmail.com>
2022-06-07 17:11:28 +02:00
Luiz Angelo Daros de Luca
8121e7dd75 realtek: add reset button for D-Link DGS-1210-28
Tested in a DGS-1210-28 F3, both triggering failsafe and reboot.

Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Reviewed-by: Robert Marko <robimarko@gmail.com>
2022-06-07 17:11:28 +02:00
John Audia
f800f8d6fc kernel: bump 5.10 to 5.10.120
All patches automatically rebased.

Build system: x86_64
Build-tested: ipq806x/R7800, x86/64

Signed-off-by: John Audia <therealgraysky@proton.me>
2022-06-06 19:20:02 +02:00
John Audia
cd634afe6c kernel: bump 5.10 to 5.10.119
Delete the crypto-lib-blake2s kmod package, as BLAKE2s is now built-in.
Patches automatically rebased.

Build system: x86_64
Build-tested: ipq806x/R7800, x86/64

Signed-off-by: John Audia <therealgraysky@proton.me>
2022-06-06 19:20:02 +02:00
Raylynn Knight
b515ad10a6 realtek: add support for ZyXEL GS1900-24E
The ZyXEL GS1900-24E is a 24 port gigabit switch similar to other GS1900
switches.

Specifications
--------------
* Device:    ZyXEL GS1900-24E
* SoC:       Realtek RTL8382M 500 MHz MIPS 4KEc
* Flash:     16 MiB Macronix MX25L12835F
* RAM:       128 MiB DDR2 SDRAM Nanya NT5TU128M8GE
* Ethernet:  24x 10/100/1000 Mbps
* LEDs:      1 PWR LED (green, not configurable)
             1 SYS LED (green, configurable)
             24 ethernet port link/activity LEDs (green, SoC controlled)
* Buttons:   1 "RESET" button on front panel
* Switch:    1 Power switch on rear of device
* Power      120-240V AC C13
* UART:      1 serial header (JP2) with populated standard pin connector on
             the left side of the PCB.
             Pinout (front to back):
             + Pin 1 - VCC marked with white dot
             + Pin 2 - RX
             + Pin 3 - TX
             + PIn 4 - GND

Serial connection parameters:  115200 8N1.

Installation
------------

OEM upgrade method:

* Log in to OEM management web interface
* Navigate to Maintenance > Firmware
* Select the HTTP radio button
* Select the Active radio button
* Use the browse button to locate the
realtek-rtl838x-zyxel_gs1900-24e-initramfs-kernel.bin
file and select open so File Path is updated with filename.
* Select the Apply button. Screen will display "Prepare
for firmware upgrade ...".
*Wait until screen shows "Do you really want to reboot?"
then select the OK button
* Once OpenWrt has booted, scp the sysupgrade image to /tmp and flash it:
   > sysupgrade -n /tmp/realtek-rtl838x-zyxel_gs1900-24e-squashfs-sysupgrade.bin
   it may be necessary to restart the network (/etc/init.d/network restart) on
   the running initramfs image.

U-Boot TFTP method:

* Configure your client with a static 192.168.1.x IP (e.g. 192.168.1.10).
* Set up a TFTP server on your client and make it serve the initramfs image.
* Connect serial, power up the switch, interrupt U-boot by hitting the
  space bar, and enable the network:
   > rtk network on
* Since the GS1900-24E is a dual-partition device, you want to keep the OEM
  firmware on the backup partition for the time being. OpenWrt can only boot
  from the first partition anyway (hardcoded in the DTS). To make sure we are
  manipulating the first partition, issue the following commands:
  > setsys bootpartition 0
  > savesys
* Download the image onto the device and boot from it:
   > tftpboot 0x84f00000 192.168.1.10:openwrt-realtek-rtl838x-zyxel_gs1900-24e-initramfs-kernel.bin
   > bootm
* Once OpenWrt has booted, scp the sysupgrade image to /tmp and flash it:
   > sysupgrade -n /tmp/openwrt-realtek-rtl838x-zyxel_gs1900-24e-squashfs-sysupgrade.bin
   it may be necessary to restart the network (/etc/init.d/network restart) on
   the running initramfs image.

Signed-off-by: Raylynn Knight <rayknight@me.com>
2022-06-06 10:30:50 +02:00
Sander Vanheule
bde6311569 realtek: don't unmask non-maskable GPIO IRQs
On uniprocessor builds, for_each_cpu(cpu, mask) will assume 'mask'
always contains exactly one CPU, and ignore the actual mask contents.
This causes the loop to run, even when it shouldn't on an empty mask,
and tries to access an uninitialised pointer.

Fix this by wrapping the loop in a cpumask_empty() check, to ensure it
will not run on uniprocessor builds if the CPU mask is empty.

Fixes: af6cd37f42 ("realtek: replace RTL93xx GPIO patches")
Reported-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Reported-by: Robert Marko <robimarko@gmail.com>
Tested-by: Robert Marko <robimarko@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-05-30 07:21:03 +02:00
Sander Vanheule
af6cd37f42 realtek: replace RTL93xx GPIO patches
Patches to support the SoC's GPIO controller for RTL930x and RTL931x
devices have been accepted upstream. Replace the current preliminary
patch with the upstream ones, excluding devictree binding changes.

The updated patches add GPIO IRQ balancing support on RTL930x, but this
cannot be used until these devices also support SMP.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-05-22 08:46:50 +02:00
Tony Ambardar
76fae1d169 config: limit CONFIG_DEBUG_INFO to top-level generic configs
Remove redundant target-level entries, noting that these settings will be
configured from "Kernel build options" of Kconfig.

Signed-off-by: Tony Ambardar <itugrok@yahoo.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
[remove from new configs introduced after patch submission]
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
2022-05-18 13:32:06 +03:00
John Audia
8592df67f4 kernel: bump 5.10 to 5.10.114
All patches automatically rebased.

Build system: x86_64
Build-tested: bcm2711/RPi4B
Run-tested: bcm2711/RPi4B

Signed-off-by: John Audia <therealgraysky@proton.me>
2022-05-16 20:26:38 +02:00
Birger Koblitz
d1b824650f realtek: do not reset SerDes on link change
Do not reset the RTL930x SerDes on link changes, instead set up
the SDS with internal PHYs for the SFP+ ports only.
This fixes the 8 1GBit ports on the Zyxel XGS1250 which
do not work without this patch.

A complete SerDes reset was performed on all SerDes links. For copper
1Gbit ports, this is commonly a single XGMII link to an RTL8218D. There
is however no support for setting up the XGMII link on RTL9300/RTL9310,
thereby wiping the (RX/TX) setup done by u-boot and breaking the 1GBit
ports. No SerDes reset should be done for these links.

The handling of SGMII/HiSGMII, 1000BX or 10GR links is actually entirely
different. All these modes need to be suitably RX calibrated and the
pre- main and post- amplifiers set up properly for TX.

The 10GBit SFP+ fiber links are recalibrated instead of reset, which
e.g. is necessary when someone pulls a module out and puts another in.
This makes swapping out 10GBit fiber modules possible. 1GBit modules are
not yet supported, nor any modules with an internal phy.

Tested-by: Stijn Segers <foss@volatilesystems.org>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
[rewrite commit message based on discussion]
Link: http://lists.infradead.org/pipermail/openwrt-devel/2022-May/038623.html
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-05-11 22:23:50 +02:00
Birger Koblitz
98bb26f9f7 realtek: Trap all frames with switch as destination to CPU-port
This fixes a bug where frames sent to the switch itself were
flooded to all ports unless the MAC address of the CPU-port
was learned otherwise.

Tested-by: Wenli Looi <wlooi@ucalgary.ca>
Tested-by: Bjørn Mork <bjorn@mork.no>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
[fix code formatting]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-05-08 10:05:14 +02:00
Raylynn Knight
580723e86a realtek: add support for ZyXEL GS1900-16
The ZyXEL GS1900-16 is a 16 port gigabit switch similar to other GS1900 switches.

Specifications
--------------
* Device:    ZyXEL GS1900-16
* SoC:       Realtek RTL8382M 500 MHz MIPS 4KEc
* Flash:     16 MiB Macronix MX25L12835F
* RAM:       128 MiB DDR2 SDRAM Nanya NT5TU128M8HE
* Ethernet:  16x 10/100/1000 Mbps
* LEDs:      1 PWR LED (green, not configurable)
             1 SYS LED (green, configurable)
             16 ethernet port link/activity LEDs (green, SoC controlled)
* Buttons:   1 "RESET" button on front panel
* Power      120-240V AC C13
* UART:      1 serial header (J12) with populated standard pin connector on
             the right back of the PCB.
             Pinout (front to back):
             + Pin 1 - VCC marked with white dot
             + Pin 2 - RX
             + Pin 3 - TX
             + PIn 4 - GND

Serial connection parameters:  115200 8N1.

Installation
------------

OEM upgrade method:

* Log in to OEM management web interface
* Navigate to Maintenance > Firmware
* Select the HTTP radio button
* Select the Active radio button
* Use the browse button to locate the
realtek-generic-zyxel_gs1900-16-initramfs-kernel.bin
file amd select open so File Path is update with filename.
* Select the Apply button. Screen will display "Prepare
for firmware upgrade ...".
*Wait until screen shows "Do you really want to reboot?"
then select the OK button
* Once OpenWrt has booted, scp the sysupgrade image to /tmp and flash it:
   > sysupgrade -n /tmp/realtek-generic-zyxel_gs1900-16-squashfs-sysupgrade.bin
   it may be necessary to restart the network (/etc/init.d/network restart) on
   the running initramfs image.

U-Boot TFTP method:

* Configure your client with a static 192.168.1.x IP (e.g. 192.168.1.10).
* Set up a TFTP server on your client and make it serve the initramfs image.
* Connect serial, power up the switch, interrupt U-boot by hitting the
  space bar, and enable the network:
   > rtk network on
* Since the GS1900-16 is a dual-partition device, you want to keep the OEM
  firmware on the backup partition for the time being. OpenWrt can only boot
  from the first partition anyway (hardcoded in the DTS). To make sure we are
  manipulating the first partition, issue the following commands:
  > setsys bootpartition 0
  > savesys
* Download the image onto the device and boot from it:
   > tftpboot 0x84f00000 192.168.1.10:openwrt-realtek-generic-zyxel_gs1900-16-initramfs-kernel.bin
   > bootm
* Once OpenWrt has booted, scp the sysupgrade image to /tmp and flash it:
   > sysupgrade -n /tmp/openwrt-realtek-generic-zyxel_gs1900-16-squashfs-sysupgrade.bin
   it may be necessary to restart the network (/etc/init.d/network restart) on
   the running initramfs image.

Signed-off-by: Raylynn Knight <rayknight@me.com>
[removed duplicate patch title, align RAM specification]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-05-07 17:23:45 +02:00
Martin Kennedy
a5ac8ad0ba realtek: add ZyXEL GS1900-24HP v1 support
The ZyXEL GS1900-24HP v1 is a 24 port PoE switch with two SFP ports,
similar to the other GS1900 switches.

Specifications
--------------
* Device:    ZyXEL GS1900-24HP v1
* SoC:       Realtek RTL8382M 500 MHz MIPS 4KEc
* Flash:     16 MiB
* RAM:       Winbond W9751G8KB-25 64 MiB DDR2 SDRAM
* Ethernet:  24x 10/100/1000 Mbps, 2x SFP 100/1000 Mbps
* LEDs:
  * 1 PWR LED (green, not configurable)
  * 1 SYS LED (green, configurable)
  * 24 ethernet port link/activity LEDs (green, SoC controlled)
  * 24 ethernet port PoE status LEDs
  * 2 SFP status/activity LEDs (green, SoC controlled)
* Buttons:
  * 1 "RESET" button on front panel (soft reset)
  * 1 button ('SW1') behind right hex grate (hardwired power-off)
* PoE:
  * Management MCU: ST Micro ST32F100 Microcontroller
  * 6 BCM59111 PSE chips
  * 170W power budget
* Power:     120-240V AC C13
* UART:      Internal populated 10-pin header ('J5') providing RS232;
             connected to SoC UART through a TI or SIPEX 3232C for voltage
             level shifting.

* 'J5' RS232 Pinout (dot as pin 1):
  2) SoC RXD
  3) GND
  10) SoC TXD

Serial connection parameters: 115200 8N1.

Installation
------------

OEM upgrade method:

* Log in to OEM management web interface

* Navigate to Maintenance > Firmware > Management

* If "Active Image" has the first option selected, OpenWrt will need to be
  flashed to the "Active" partition. If the second option is selected,
  OpenWrt will need to be flashed to the "Backup" partition.

* Navigate to Maintenance > Firmware > Upload

* Upload the openwrt-realtek-rtl838x-zyxel_gs1900-24hp-v1-initramfs-kernel.bin
  file by your preferred method to the previously determined partition.
  When prompted, select to boot from the newly flashed image, and reboot
  the switch.

* Once OpenWrt has booted, scp the sysupgrade image to /tmp and flash it:

  > sysupgrade /tmp/openwrt-realtek-rtl838x-zyxel_gs1900-24hp-v1-squashfs-sysupgrade.bin

U-Boot TFTP method:

* Configure your client with a static 192.168.1.x IP (e.g. 192.168.1.10).

* Set up a TFTP server on your client and make it serve the initramfs
  image.

* Connect serial, power up the switch, interrupt U-boot by hitting the
  space bar, and enable the network:

  > rtk network on

* Since the GS1900-24HP v1 is a dual-partition device, you want to keep the
  OEM firmware on the backup partition for the time being. OpenWrt can
  only be installed in the first partition anyway (hardcoded in the
  DTS). To ensure we are set to boot from the first partition, issue the
  following commands:

  > setsys bootpartition 0
  > savesys

* Download the image onto the device and boot from it:

  > tftpboot 0x81f00000 192.168.1.10:openwrt-realtek-rtl838x-zyxel_gs1900-24hp-v1-initramfs-kernel.bin
  > bootm

* Once OpenWrt has booted, scp the sysupgrade image to /tmp and flash it:

  > sysupgrade /tmp/openwrt-realtek-rtl838x-zyxel_gs1900-24hp-v1-squashfs-sysupgrade.bin

Signed-off-by: Martin Kennedy <hurricos@gmail.com>
[Add info on PoE hardware to commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-04-16 17:26:56 +02:00
Hauke Mehrtens
34fb36e165 realtek: Fix tc default package
The tc package does not exits any more, it was split into tc-tiny,
tc-full and tc-bpf. Include tc-bpf by default into realtek images.

This increases the compressed image size by about 232KBytes.

Tested-by: Stijn Segers <foss@volatilesystems.org>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2022-03-29 13:43:01 +02:00
Hauke Mehrtens
469030659c realtek: Use firewall4
The realtek target is not a router, but basic device, see DEVICE_TYPE.
The basic device type does not come with firewall by default, see
include/target.mk for details. The realtek target extended
DEFAULT_PACKAGES manually with firewall.

This changes the defaults to take firewall4 and nftables instead of
firewall and iptables. This also adds the additional package
kmod-nft-offload.

The only difference to the router type is the missing ppp,
ppp-mod-pppoe, dnsmasq and odhcpd-ipv6only package.

This increases the compressed image size by about 422KBytes.

Tested-by: Stijn Segers <foss@volatilesystems.org>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2022-03-29 13:42:56 +02:00
Hauke Mehrtens
2acebbdcaa realtek: Remove dnsmasq and odhcpd-ipv6only from default
Do not include the dnsmasq and odhcpd-ipv6only package by default any
more. These services are not needed on a switch. If someone needs this
it is still possible to use opkg or image builder to add them.

This decreases the compressed image size by about 165KBytes.

Tested-by: Stijn Segers <foss@volatilesystems.org>
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
2022-03-29 13:42:29 +02:00
John Audia
b04d38a2ea kernel: bump 5.10 to 5.10.106
All patches automatically rebased.

Build system: x86_64
Build-tested: bcm2711/RPi4B, mt7622/RT3200
Run-tested: bcm2711/RPi4B, mt7622/RT3200

Signed-off-by: John Audia <graysky@archlinux.us>
2022-03-19 16:13:58 +01:00
INAGAKI Hiroshi
e83ab243be realtek: add support for Panasonic Switch-M8eG PN28080K
Panasonic Switch-M8eG PN28080K is a 8 + 1 port gigabit switch, based on
RTL8380M.

Specification:

- SoC		: Realtek RTL8380M
- RAM		: DDR3 128 MiB (Winbond W631GG8KB-15)
- Flash		: SPI-NOR 32 MiB (Macronix MX25L25635FMI-10G)
- Ethernet	: 10/100/1000 Mbps x8 + 1
  - port 1-8	: TP, RTL8218B (SoC)
  - port 9	: SFP, RTL8380M (SoC)
- LEDs/Keys	: 7x / 1x
- UART		: RS-232 port on the front panel (connector: RJ-45)
  - 3:TX, 4:GND, 5:GND, 6:RX (pin number: RJ-45)
  - 9600n8
- Power		: 100-240 VAC, 50/60 Hz, 0.5 A
  - Plug	: IEC 60320-C13
- Stock OS	: VxWorks based

Flash instruction using initramfs image:

1.  Prepare the TFTP server with the IP address 192.168.1.111
2.  Rename the OpenWrt initramfs image to "0101A8C0.img" and place it to
    the TFTP directory
3.  Download the official upgrading firmware (ex: pn28080k_v30000.rom)
    and place it to the TFTP directory
4.  Boot M8eG and interrupt the U-Boot with Ctrl + C keys
5.  Execute the following commands and boot with the OpenWrt initramfs
    image

    rtk network on
    tftpboot 0x81000000
    bootm

6.  Backup mtdblock files to the computer by scp or anything and reboot
7.  Interrupt the U-Boot and execute the following commands to re-create
    filesystem in the flash

    ffsmount c:/
    ffsfmt c:/

    this step takes a long time, about ~ 4 mins

8.  Execute the following commands to put the official images to the
    filesystem

    updatert <official image>

    example:

      updatert pn28080k_v30000.rom

    this step takes about ~ 40 secs

9.  Set the environment variables of the U-Boot by the following commands

    setenv loadaddr 0xb4e00000
    setenv bootcmd bootm
    saveenv

10: Download the OpenWrt initramfs image and boot with it

    tftpboot 0x81000000 0101A8C0.img
    bootm

11: On the initramfs image, download the sysupgrade image and perform
    sysupgrade with it

    sysupgrade <imagename>

12: Wait ~ 120 seconds to complete flashing

Note:

- "Switch-M8eG" is a model name, and "PN28080K" is a model number.
  Switch-M8eG has an another (old) model number ("PN28080"), it's not a
  Realtek based hardware.

- Switch-M8eG has a "POWER" LED (Green), but it's not connected to any
  GPIO pin.

- The U-Boot checks the runtime images in the flash when booting and
  fails to execute anything in "bootcmd" variable if the images are not
  exsisting.

- A filesystem is formed in the flash (0x100000-0x1DFFFFF) on the stock
  firmware and it includes the stock images, configuration files and
  checksum files. It's unknown format, can't be managed on the OpenWrt.
  To get the enough space for OpenWrt, move the filesystem to the head
  of "fs_reserved" partition by execution of "ffsfmt" and "updatert".

- On the other devices in the same series of Switch-M8eG PN28080K, the
  INT pin on the PCA9555 is not connected to anywhere.

Back to the stock firmware:

1. Delete "loadaddr" variable and set "bootcmd" to the original value

   on U-Boot:

     setenv loadaddr
     setenv bootcmd 'bootm 0x81000000'

   on OpenWrt:

     fw_setenv loadaddr
     fw_setenv bootcmd 'bootm 0x81000000'

2. Perform reset or reboot

  on U-Boot:

    reset

  on OpenWrt:

    reboot

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Reviewed-by: Sander Vanheule <sander@svanheule.net>
2022-03-13 19:54:57 +01:00
INAGAKI Hiroshi
da1347d6d6 realtek: enable pca953x driver for rtl838x subtarget
The system status LED on Panasonic Switch-M8eG PN28080K is connected to
a PCA9539PW. To use the LED as a status LED of OpenWrt while booting,
enable the pca953x driver and built-in to the kernel.
Also enable CONFIG_GPIO_PCA953X_IRQ to use interrupt via RTL83xx GPIO.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Acked-by: Sander Vanheule <sander@svanheule.net>
2022-03-13 19:54:57 +01:00
Martin Kennedy
d1a8690742 realtek: add ZyXEL GS1900-24 v1 support
The ZyXEL GS1900-24 v1 is a 24 port switch with two SFP ports, similar to
the other GS1900 switches.

Specifications
--------------
* Device:    ZyXEL GS1900-24 v1
* SoC:       Realtek RTL8382M 500 MHz MIPS 4KEc
* Flash:     16 MiB
* RAM:       Winbond W9751G8KB-25 64 MiB DDR2 SDRAM
* Ethernet:  24x 10/100/1000 Mbps, 2x SFP 100/1000 Mbps
* LEDs:
  * 1 PWR LED (green, not configurable)
  * 1 SYS LED (green, configurable)
  * 24 ethernet port link/activity LEDs (green, SoC controlled)
  * 2 SFP status/activity LEDs (green, SoC controlled)
* Buttons:
  * 1 "RESET" button on front panel (soft reset)
  * 1 button ('SW1') behind right hex grate (hardwired power-off)
* Power:     120-240V AC C13
* UART:      Internal populated 10-pin header ('J5') providing RS232;
             connected to SoC UART through a SIPEX 3232EC for voltage
             level shifting.

* 'J5' RS232 Pinout (dot as pin 1):
  2) SoC RXD
  3) GND
  10) SoC TXD

Serial connection parameters: 115200 8N1.

Installation
------------

OEM upgrade method:

* Log in to OEM management web interface

* Navigate to Maintenance > Firmware > Management

* If "Active Image" has the first option selected, OpenWrt will need to be
  flashed to the "Active" partition. If the second option is selected,
  OpenWrt will need to be flashed to the "Backup" partition.

* Navigate to Maintenance > Firmware > Upload

* Upload the openwrt-realtek-rtl838x-zyxel_gs1900-24-v1-initramfs-kernel.bin
  file by your preferred method to the previously determined partition.
  When prompted, select to boot from the newly flashed image, and reboot
  the switch.

* Once OpenWrt has booted, scp the sysupgrade image to /tmp and flash it:

  > sysupgrade /tmp/openwrt-realtek-rtl838x-zyxel_gs1900-24-v1-squashfs-sysupgrade.bin

U-Boot TFTP method:

* Configure your client with a static 192.168.1.x IP (e.g. 192.168.1.10).

* Set up a TFTP server on your client and make it serve the initramfs
  image.

* Connect serial, power up the switch, interrupt U-boot by hitting the
  space bar, and enable the network:

  > rtk network on

> Since the GS1900-24 v1 is a dual-partition device, you want to keep the
  OEM firmware on the backup partition for the time being. OpenWrt can
  only be installed in the first partition anyway (hardcoded in the
  DTS). To ensure we are set to boot from the first partition, issue the
  following commands:

  > setsys bootpartition 0
  > savesys

* Download the image onto the device and boot from it:

  > tftpboot 0x81f00000 192.168.1.10:openwrt-realtek-rtl838x-zyxel_gs1900-24-v1-initramfs-kernel.bin
  > bootm

* Once OpenWrt has booted, scp the sysupgrade image to /tmp and flash it:

  > sysupgrade /tmp/openwrt-realtek-rtl838x-zyxel_gs1900-24-v1-squashfs-sysupgrade.bin

Signed-off-by: Martin Kennedy <hurricos@gmail.com>
2022-03-13 19:24:13 +01:00
INAGAKI Hiroshi
7b19770525 realtek: add support for I-O DATA BSH-G24MB
I-O DATA BSH-G24MB is a 24 port gigabit switch, based on RTL8382M.

Specification:

- SoC		: Realtek RTL8382M
- RAM		: DDR2 128 MiB (Nanya NT5TU128M8HE-AC)
- Flash		: SPI-NOR 16 MiB (Macronix MX25L12835FM2I-10G)
- Ethernet	: 10/100/1000 Mbps x24
  - port 1-8	: RTL8218B
  - port 9-16	: RTL8218B (SoC)
  - port 17-24	: RTL8218B
- LEDs/Keys	: 2x, 1x
- UART		: pin header on PCB
  - JP2: 3.3V, TX, RX, GND from rear side
  - 115200n8
- Power		: 100 VAC, 50/60 Hz
  - Plug	: IEC 60320-C13

Flash instruction using sysupgrade image:

1. Boot BSH-G24MB normally
2. Connect BSH-G24MB to the DHCP enabled network
3. Find the device's IP address and open the WebUI and login
   Note: by default, the device obtains IP address from DHCP server of
         the network
4. Open firmware update page ("ファームウェア アップデート")
5. Rename the OpenWrt sysupgrade image to "bsh-g24mb_v100.image" and
   select it
6. Press apply ("適用") button to perform update
7. Wait ~150 seconds to complete flashing

Note:

- BSH-G24MB has a power-related LED ("電源"), but it's not connected to
  the GPIO of the SoC or RTL8231 and cannot be controlled. Instead of
  it, use system status LED on other than running-state.

- "sys_loop" LED indicates system status and loop-detection status in
  stock firmware.

- BSH-G24MB has 2x os-image partitions named as "RUNTIME"/"RUNTIME2" in
  16 MiB SPI-NOR flash and the size of image per partition is only
  6848 KiB. The secondary image is never used on stock firmware, so also
  use it on OpenWrt to get more space.

Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
2022-03-07 21:44:53 +01:00
Bjørn Mork
0890fb2df4 realtek: net: dsa: configure better brport flags when ports leave the bridge
Ensures that the DSA driver sets exactly the same default flags as the
bridge when a port joins or leaves.  Without this we end up with a
confusing flag mismatch, where DSA and bridge ports use different sets
of flags.

This is critical as the "learning" mismatch will be harmful to the
network, causing all traffic to be flooded on all ports.

The original commit was buggy, trying to set the flags one-by-one in a
loop.  This was not supported by the API and the end result was that
all but the last flag were cleared.  This bug was implicitly fixed
upstream by commit e18f4c18ab5b ("net: switchdev: pass flags and mask
to both {PRE_,}BRIDGE_FLAGS attributes").

This is a minimum temporary stop measure fix for the critical lack of
"learning" only.  The major API change associated with a full v5.12+
backport is neither required nor wanted. A simpler fix, moving the
call to dsa_port_bridge_flags() out of the loop,  has therefore been
merged into this modified backport.

Fixes: afa3ab54c0 ("realtek: Backport bridge configuration for DSA")
Signed-off-by: Bjørn Mork <bjorn@mork.no>
Acked-by: Daniel Golle <daniel@makrotopia.org>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
[fix typos in commit message]
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
2022-03-06 22:01:04 +02:00
John Audia
0989b7ad3a kernel: bump 5.10 to 5.10.102
Removed upstreamed:
	bcm4908/patches-5.10/180-i2c-brcmstb-fix-support-for-DSL-and-CM-variants.patch[1]

All other patches automatically rebased.

1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.102&id=f333c1916fd6b55900029bf8f918cc00009e2111

Build system: x86_64
Build-tested: bcm2711/RPi4B, mt7622/RT3200
Run-tested: bcm2711/RPi4B, mt7622/RT3200

Signed-off-by: John Audia <graysky@archlinux.us>
2022-03-01 21:38:36 +01:00
Sander Vanheule
66d8db01cc realtek: remove debugging code from timer
Remove some (dead) debugging code from the Realtek timer to clean up the
sources of this driver.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-02-20 16:23:58 +00:00
Sander Vanheule
9db651f4a2 realtek: use DT provided address for timers
The I/O base address for the timers was hardcoded into the driver,
or derived from the HW IRQ number as an even more horrible hack. All
supported SoC families have these timers, but with hardcoded addresses
the code cannot be reused right now.

Request the timer's base address from the DT specification, and store it
in a private struct for future reference.

Matching the second interrupt specifier, the address range for the
second timer is added to the DT specification.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-02-20 16:23:58 +00:00
Sander Vanheule
71810eb068 realtek: clean up RTL930x timer DT node
The Realtek timer node for RTL930x doesn't have any child nodes, making
the use of '#address-cells' quite pointless. It is also not an interrupt
controller, meaning it makes no sense to define '#interrupt-cells'.

The I/O address for this node is also wrong, but this is hidden by the
fact that the driver associated with this node bypasses the usual DT
machinery and does it's own thing. Correct the address to have a sane
value, even though it isn't actually used.

Fixes: a75b9e3ecb ("realtek: Adding RTL930X sub-target")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-02-20 16:23:58 +00:00
Sander Vanheule
fa20f2bfc7 realtek: ZyXEL GS1900-48: fix system LED polarity
When driven by a GPIO pin, the system LED needs to be configured as
active high. Otherwise the LED switches off after booting and
initialisation.

Fixes: 47f5a0a3ee ("realtek: Add support for ZyXEL GS1900-48 Switch")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-02-20 16:23:55 +00:00
Sander Vanheule
66140820e1 realtek: ZyXEL GS1900-48: drop status from gpio1
The default value for a DT node's status property is already "okay", so
there's no need to specify it again. Drop the status property to clean
up the DTS.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-02-20 16:23:55 +00:00
Sander Vanheule
a39fbaf23a realtek: use higher priority for timer interrupts
The assigned output index for the event timers was quite low, lower even
than the ethernet interrupt. This means that high network load could
preempt timer interrupts, possibly leading to all sorts of strange
behaviour.

Increase the interrupt output index of the event timers to 5, which is
the highest priority output and corresponds to the (otherwise unused)
MIPS CPU timer interrupt.

Fixes: a75b9e3ecb ("realtek: Adding RTL930X sub-target")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-02-20 16:23:55 +00:00
Sander Vanheule
4b31717fb0 realtek: move RTL8231 definitions to board files
The RTL8231 is an external chip, and not part of the SoC. That means
it is more appropriate to define it in the board specific (base) files,
instead of the DT include for the SoC itself.

Moving the RTL8231 definition also ensures that boards with no GPIO
expander, or an alternative one, don't have a useless gpio1 node label
defined.

Tested on a Netgear GS110TPPv1.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-02-20 16:23:55 +00:00
Sander Vanheule
004d4d66c8 realtek: fix node addresses for RTL839x
The address in some node names doesn't match the actual offset specified
in the DT node. Update the names to fix this.

While fixing the node names, also drop the unused node labels.

Fixes: 0a7565e536 ("realtek: Update rtl839x.dtsi for realtek,rtl-intc, new gpio controller remove RTL8231 node")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-02-20 16:23:55 +00:00
Sander Vanheule
1ca081000a realtek: consolidate bootargs again
Bootargs for devices in the realtek target were previously consolidated
in commit af2cfbda2b ("realtek: Consolidate bootargs"), since all
devices currently use the same arguments.

Commit a75b9e3ecb ("realtek: Adding RTL930X sub-target") reverted this
without any argumentation, so let's undo that.

Commit 0b8dfe0851 ("realtek: Add RTL931X sub-target") introduced the
old bootargs also for RTL931x, without providing any actual device
support. Until that is done, let's assume vendors will have done what
they did before, and use a baud rate of 115200.

Fixes: a75b9e3ecb ("realtek: Adding RTL930X sub-target")
Signed-off-by: Sander Vanheule <sander@svanheule.net>
2022-02-20 16:23:55 +00:00
Birger Koblitz
4d8020072e realtek: fix locking bug in rtl838x_hw_receive()
A Locking bug in the packet receive path was introduced with PR
#4973. The following patch prevents the driver from locking
after a few minutes with an endless flow of

[ 1434.185085] rtl838x-eth 1b00a300.ethernet eth0: Ring contention: r: 0, last a28000f4, cur a28000f8
[ 1434.208971] rtl838x-eth 1b00a300.ethernet eth0: Ring contention: r: 0, last a28000f4, cur a28000fc
[ 1434.794800] rtl838x-eth 1b00a300.ethernet eth0: Ring contention: r: 0, last a28000f4, cur a28000fc
[ 1435.049187] rtl838x-eth 1b00a300.ethernet eth0: Ring contention: r: 0, last a28000f4, cur a28000fc

Signed-off-by: Bjørn Mork <bjorn@mork.no>
Signed-off-by: Birger Koblitz <mail@birger-koblitz.de>
2022-02-18 12:35:03 +00:00
Sander Vanheule
a93dfff10e realtek: add RTL8231 chip detection
When initialising the driver, check if the RTL8231 chip is actually
present at the specified address. If the READY_CODE value does not match
the expected value, return -ENXIO to fail probing.

This should help users to figure out which address an RTL8231 is
configured to use, if measuring pull-up/-down resistors is not an
option.

On an unsuccesful probe, the driver will log:
    [    0.795364] Probing RTL8231 GPIOs
    [    0.798978] rtl8231_init called, MDIO bus ID: 30
    [    0.804194] rtl8231-gpio rtl8231-gpio: no device found at bus address 30

When a device is found, only the first two lines will be logged:
    [    0.453698] Probing RTL8231 GPIOs
    [    0.457312] rtl8231_init called, MDIO bus ID: 31

Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
2022-02-17 19:11:42 +02:00
Sander Vanheule
44f7cfd760 realtek: always require SMI bus ID for RTL8231
The SMI bus ID for RTL8231 currently defaults to 0, and can be
overridden from the devicetree. However, there is no value check on the
DT-provided value, aside from masking which would only cause value
wrap-around.

Change the driver to always require the "indirect-access-bus-id"
property, as there is no real reason to use 0 as default, and perform a
sanity check on the value when probing. This allows the other parts of
the driver to be simplified a bit.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
2022-02-17 19:11:37 +02:00
Sander Vanheule
5da2e0cc20 realtek: use automatic GPIO numbering for RTL8231
Set the gpio_chip.base to -1 to use automatic GPIO line indexing.
Setting base to 0 or a positive number is deprecated and should not be
used.

Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
2022-02-17 19:11:33 +02:00
Sander Vanheule
851212a714 realtek: fix RTL8231 gpio count
The RTL8231's gpio_chip.ngpio was set to 36, which is the largest valid
GPIO index. Fix the allowed number of GPIOs by setting ngpio to 37, the
actual line count.

Reported-by: INAGAKI Hiroshi <musashino.open@gmail.com>
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
2022-02-17 19:11:17 +02:00
Daniel Golle
eef7f17652 realtek: rtl83xx-phy: abstract and document PHY features
Replace magic values with more self-descriptive code now that I start
to understand more about the design of the PHY (and MDIO controller).

Remove one line before reading RTL8214FC internal PHY id which turned
out to be a no-op and can hence safely be removed (confirmed by
INAGAKI Hiroshi[1])

[1]: df8e6be59a (r66890713)

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
2022-02-17 15:37:03 +00:00
Birger Koblitz
68c66b0fa3 realtek: fix locking issues
Fixe a coupld of locking issues found by applying lock
debugging to the code.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Daniel Golle
b53202a8c3 realtek: switch to use generic MDIO accessor functions
Instead of directly calling SoC-specific functions in order to access
(paged) MII registers or MMD registers, create infrastructure to allow
using the generic phy_*, phy_*_paged and phy_*_mmd functions.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
2022-02-17 15:21:47 +00:00
Daniel Golle
af93bf6129 realtek: implement Clause-45 MDIO write on rtl931x
* Add missing Clause-45 write support for rtl931x
 * Switch to use helper functions in all Clause-45 access functions to
   make the code more readable.
 * More meaningful/unified debugging output (dynamic kprintf)

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
2022-02-17 15:21:47 +00:00
Daniel Golle
854458f986 realtek: backport Clause-45 MDIO helper functions
Import commit ("c6af53f038aa3 net: mdio: add helpers to extract clause
45 regad and devad fields") from Linux 5.17 to allow making the MDIO
code in the ethernet driver more readable.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
2022-02-17 15:21:47 +00:00
Birger Koblitz
0538dc693b realtek: add support for port led configuration on RTL93XX
Using the led-set attribute of a port in the dts we allow configuration
of the port leds. Each led-set is being defined in the led-set configuration
of the .dts, giving a specific configuration to steer the port LEDs via a serial
connection.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
caaac9ab3b realtek: Add support for the RTL8221B PHY
The RTL8221B PHY is a newer version of the RTL8226, also supporting
2.5GBit Ethernet. It is found with RTL931X devices such as the
EdgeCore ECS4125-10P

Signed-off-by: Sebastian Gottschall <s.gottschall@dd-wrt.com>
Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00
Birger Koblitz
08cf48c344 realtek: Add specific PHY polling options to support the Zyxel XGS1250/XGS1210
Both the Aquantia AQR113c and the RTL8226 PHYs in the Zyxel XGS1250 and the
Zyxel XGS1210 require special polling configuration settings in the
RTL930X_SMI_10GPHY_POLLING_REGxx_CFG configuration registers. Set them.
Additionally, for RTL 1GBit phys set the RTL930X_SMI_PRVTE_POLLING_CTRL bits
in the poll mask.

Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
2022-02-17 15:21:47 +00:00