This commit adds support for the OCEDO Koala
SOC: Qualcomm QCA9558 (Scorpion)
RAM: 128MB
FLASH: 16MiB
WLAN1: QCA9558 2.4 GHz 802.11bgn 3x3
WLAN2: QCA9880 5 GHz 802.11nac 3x3
INPUT: RESET button
LED: Power, LAN, WiFi 2.4, WiFi 5, SYS
Serial: Header Next to Black metal shield
Pinout is 3.3V - GND - TX - RX (Arrow Pad is 3.3V)
The Serial setting is 115200-8-N-1.
Tested and working:
- Ethernet
- 2.4 GHz WiFi
- 5 GHz WiFi
- TFTP boot from ramdisk image
- Installation via ramdisk image
- OpenWRT sysupgrade
- Buttons
- LEDs
Installation seems to be possible only through booting an OpenWRT
ramdisk image.
Hold down the reset button while powering on the device. It will load a
ramdisk image named 'koala-uImage-initramfs-lzma.bin' from 192.168.100.8.
Note: depending on the present software, the device might also try to
pull a file called 'koala-uimage-factory'. Only the name differs, it
is still used as a ramdisk image.
Wait for the ramdisk image to boot. OpenWRT can be written to the flash
via sysupgrade or mtd.
Due to the flip-flop bootloader which we not (yet) support, you need to
set the partition the bootloader is selecting. It is possible from the
initramfs image with
> fw_setenv bootcmd run bootcmd_1
Afterwards you can reboot the device.
Signed-off-by: David Bauer <mail@david-bauer.net>
Bit 8/12 of reset controller which is marked as PHY_RESET/SWITCH_RESET
in datasheets will trigger either a reset for builtin switch or assert
an external ETH0_RESET_L/ETH1_RESET_L pin, which are usually connected
to external PHY/switch. None of them should be triggered every time an
interface is brought up in ethernet driver.
Remove PHY reset support from ag71xx and definition for them in dtsi.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Buffalo BHR-4GRV2 is a wired router, based on Qualcomm Atheros
QCA9558.
Ported from ar71xx target.
Specification:
- Qualcomm Atheros QCA9558
- 64 MB of RAM
- 16 MB of Flash
- 5x 10/100/1000 Ethernet
- QCA8337N
- 4x LEDs, 2x keys
- UART header on PCB
- Vcc, TX, RX, GND from LED side
- 115200n8
Flash instruction using factory image:
1. Connect the computer to the LAN port of BHR-4GRV2
2. Connect power cable to BHR-4GRV2 and turn on it
3. Access to "http://192.168.12.1/" and open firmware update
page ("ファームウェア更新")
4. Select the OpenWrt factory image and click update ("更新実行")
button
5. Wait ~120 seconds to complete flashing
Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
This adds PLL settings for the ethernet ports of the TP-Link TL-WR1043
v2/v3 and the Openmesh OM5P-AC-v2.
We also change the PLL-settings in the qca9557.dtsi to match the ones
used as default on the ar71xx target.
As of 4b9680f138 those devices have broken ethernet ports as the default
PLL settings defined in the QCA9557.dtsi are applied which are off for
those devices.
Signed-off-by: David Bauer <mail@david-bauer.net>
commit 4b9680f fixed pll settings and the correct pll set
by bootloader is overrided by value in qca9557.dtsi which
is incorrect for Archer C7 and breaks ethernet. Add pll
values for archer c7 to fix ethernet connection.
This individual pll tweak has been cherry picked from github pr 1260
which changes a couple of things in a single commit and should be
ideally split. This commit get archer v7 back and working.
Tested: archer c7 v2
Original combined commit authored by:
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
c7 fix only split out by:
Signed-off-by: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk>
The QCA9557 dtsi is currently missing pll-handle and pll-regs for both
eth0 and eth1, therefore PLL settings won't be applied. This commit
fixes this behavior.
Signed-off-by: David Bauer <mail@david-bauer.net>
Including the tl-wdr3600 image build code just to overwrite most of it
doesn't make much sense and only makes it hard to read.
Furthermore, the tl-wdr4300 image will be marked as compatible with the
tl-wdr3600 this way.
Signed-off-by: Mathias Kresin <dev@kresin.me>
The variables are used in image build recipes and need to be marked as
per devices vars to be stored individual per image define. Otherwise
the last defined variable will be used for all boards.
Signed-off-by: Mathias Kresin <dev@kresin.me>
This patch did the following things:
1. Separate ath9k-leds out of gpio leds so that all other leds will work
before ath9k loded (e.g. during preinit/init stage).
2. Rename wps led to qss since that's how TP-Link mark it.
3. Rename LED prefix to tp-link because that dts is shared by many devices.
4. Rename to wr740n-v1 because v1 is the first and v2 just use the fw of v1.
(This will require a forced sysupgrade if you comes from
the previous wr740n v2 image.)
5. Remove SUPPORTED_DEVICES.
(tl-wr740n-v2 doesn't exist anywhere so it's useless.)
6. Add all WR741ND v1 clones found in ar71xx.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Fix all issues found by the devicetree compiler like wrong address/size
cells as well as wrong/missing/superfluous unit addresses.
Signed-off-by: Mathias Kresin <dev@kresin.me>
Use only the jedec,spi-nor compatible string. Everything else either
never worked or is only support to keep compatibility.
Signed-off-by: Mathias Kresin <dev@kresin.me>
This router is called Archer C7 and the tl was used to identify
TP-LINK. Since we have added tplink in dts/board name, the tl
prefix is useless now.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Change lan and it's LED to eth0
It's broken since c7c807cb8c
where I changed the dts but forgot to change default configurations.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
1. Swap eth0/eth1
Both devices are using AR9331, the builtin switch on AR9331 is
connected to gmac1 and gmac1 is named as eth1 in ath79.
PS: gmac1 is eth0 and gmac0 is eth1 in ar71xx because of the
reversed initialization order.
2. Fix the incorrect compatible string in dts
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
phy-handle is used to poll link status. They are useless when
we need fixed-link on these interfaces.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Without this patch you will get an error "gpio-export probe deferral
not supported" when you try to export i2c expander gpio pins.
gpio-export is probed long before i2c-bus and i2c expander are created
and it doesn't retry it so none pins are exported.
Signed-off-by: René van Dorst <opensource@vdorst.com>
apply the change to all instances of the gpio exports patch
Signed-off-by: Mathias Kresin <dev@kresin.me>
Revert 290c54473e ("ath79: fix TP-Link Archer C7 v2 wlan1 MAC address")
which obviously aims to have a distinct MAC address per interface.
Unfortunally it doesn't match what is used by the stock firmware and we
shouldn'z use MAC Adresses not reserverd for/assigned to a particular
board.
The correct MAC adress increments for this board are:
wlan0 (5GHz) : -1
wlan1 (2.4GHz) : 0
eth1 (LAN) : 0
eth0 (WAN) : 1
Fixes: FS#408
Signed-off-by: Mathias Kresin <dev@kresin.me>
The PowerCloud Systems CR3000 was a cloud-managed CPE for a now defunct
NaaS offering. It was previously supported under the ar71xx branch and
this forward ports that support with some notable differences:
1) Since reverting to stock firmware is now irrelevant there is is only
a single openwrt image generated which uses the entire flash rather than
preserving PowerCloud-specific partitions that are unneeded to openwrt--
those partitions will be erased and used by the openwrt image.
2) Rather than use a non-standard probe order for the ethernet devices,
this image uses a set of 'ip link set ethX name ethY' commands very early
in preinit (before the network is used at all), in order to have the the
switch and Wan use the same ethernet names as in previous images.
3) /etc/config/wireless will need to be regenerated as the path to the
wireless device has changed due to differences in ath79 DT for ar93x
compared to ar71xx images.
4) eth0 is wan and eth1 is lan (switch)
Signed-off-by: Daniel F. Dickinson <cshored@thecshore.com>
In the new DT-based pci-ar71xx driver, ar71xx_pci_irq_init() was being
called before populating the PCI controller's device_node struct member.
This led to no IRQ being assigned to connected PCI devices (e.g. ath9k
cards) and caused them to be non-functional aside from simply being
detected.
The previous errors encountered in dmesg were: "irq: no irq domain found
for /ahb/apb/pcie-controller@180c0000 !". /proc/interrupts listed an IRQ
of 0 for the cards.
While this has been only been tested on a yet-to-be-merged RouterStation
Pro target, it should also fix the broken wifi people have reported for
the ath79 WNDR3800 target.
Signed-off-by: Matt Merhar <mattmerhar@protonmail.com>
mdio bus isn't a standalone device on ar7240. (and maybe older SoCs?)
Use simple-mfd for ar7241 and later SoCs to get mdio1 ready before gmac0
For ar7240 and older chips, manually create platform device after
ag71xx_hw_init() in ag71xx_probe()to get mdio0 ready between
ag71xx_hw_init() and ag71xx_phy_connect().
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Allow specifying desired mdio clock frequency in dts.
Use default frequency around 5MHz for builtin switch and 2MHz for other mdio bus.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Remove mdio1 and phy1 handle. AR8327N is controlled through mdio0.
Add gmac-config for Archer C7.
Remove ucidef_set_interfaces_lan_wan. They can be determined by config_generate automatically.
The following are for adding support for WDR4900 v2/Archer C7 v1 and other
devices that shared the same machine file in ar71xx:
Move mtd partitions to archer-c7-v2.dts. Only Archer C7 v2 has 16M flash.
Flash on Archer C7 v1/TL-WDR4900 v2 is 8M.
Add label for wlan leds. The default trigger for archer c7/wdr4900 is different.
Move wlan5g led to archer-c7-v2.dts. 5G led on WDR4900 is connected to ar9380.
Move rfkill definition to archer-c7-v2.dts. There is no such a button on wdr4900 v2.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
enable mdio1 by default because mdio1 node is a subnode of eth1
and eth1 node is a "simple-mfd", which makes mdio1 disabled when
eth1 isn't enabled.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Most qca devices use 115200n8 as it's default uart baudrate.
Add 'chosen' node for qca953x like other SoCs in ath79 target.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Commit c7efc93 renamed controller name
to qca,ar9340-intc and added some functions but qca9533.dtsi was overlooked.
Correct the dtsi and adust it to the new format
Add gmac and correct reset for cascaded irq and build-in switch
Also add the reference clock to soc dtsi so we don't have to have it in every dts
Signed-off-by: Lucian Cristian <lucian.cristian@gmail.com>
Remove switch reset definition
Fix gmac compatible string (We only need SW_PHY_SWAP and SW_PHY_ADDR_SWAP on qca953x so use ar9330-gmac instead of ar9340-gmac.)
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
gmac0 is always connected to switch phy4 and mdio1 is always needed.
So add phy handle for eth0 and enable mdio1 by default.
Move fixed-link for gmac1 from device dts to ar9331.dtsi because gmac1 is always connected to builtin switch.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Enable mdio1 by default because mdio1 is needed when eth1 is enabled.
PS: If a ar9341 device has only one port and you only want to use gmac0,
change compatible of gmac1 to "syscon", "simple-mfd" in dts.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
This patch did several things:
1. Probe the builtin switch as a separated mdio device.
2. Register a separated mdio bus for builtin switch.
3. Use generic mdio read/write function instead of calling ag71xx_mdio_mii_read/write directly.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
We need to have mdio1 belonging to gmac1 initialized before gmac0.
Split it into a separated mdio device to get both mdios ready before probing gmac.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
The builtin switch has it's initial valid mac address(00:00:01:00:00:00).
Since the builtin switch is an independent device, setting mac address of gmac1 to builtin switch isn't a good idea and this makes it impossilbe to split builtin switch apart as an independent platform device.
Remove these functions and apply default VLAN during initialization as a preparation for further driver splitting.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
