The options are managed on a generic way by video packages
Additionally, only one of the currently supported boards
has a camera interface, but it requires programming
the FPGA fabric first
Signed-off-by: Luis Araneda <luaraneda@gmail.com>
The options are managed on a generic way by the sound
kmod packages
Additionally, none of the currently supported boards have
sound support out of the box, as they require programming
the FPGA fabric first
Signed-off-by: Luis Araneda <luaraneda@gmail.com>
It is a small form factor computer with rich amount of expansion ports.
Some hardware specs and supported features in this commit:
CPU: NVIDIA Tegra 2 @ 1GHz
RAM: 1GB DDR2-667
Storage: SDHC card slot
µSDHC card slot
USB to SATA bridge (depends on model)
1MB SPI NOR flash for bootloader (single partition)
LAN: RTL8111DL GbE
WIFI: RT3070 b/g/n with external antenna (depends on model)
RTC: EM3027 (mapped as rtc0; with battery backup)
Tegra 2 built-in (mapped as rtc1)
Sound: Analog/Digital (TLV320AIC23b; S/PDIF not tested)
Connectors: 4x USB 2.0
RS232 (mini serial)
HDMI
DVI-D (depends on model, not supported atm)
Extension connector (24 pin ZIF, 0.5mm pitch):
2X UART
SPI
JTAG (1.8V)
Other: power button with green led (not functional for early revisions
without programmed PMIC)
2x GPIO configurable green led
TrimSlice uses U-Boot placed in NOR flash. Boots Linux from any media
connected to USB, SATA or SD card inserted in slot. Can also boot from
TFTP. To run OpenWrt one needs to update U-Boot to fairly recent version
(the versions, pre-dts/dts provided by CompuLab won't suffice):
1. Boot TrimSlice into Your current linux distro,
2. Download trimslice-spi.img from u-boot-trimslice subdir,
3. Install mtd-utils,
4. Run following commands:
flash_erase /dev/mtd0 0 256
nandwrite /dev/mtd0 trimslice-spi.img
5. Poweroff, insert SD card with OpenWrt, boot and enjoy.
If by some obstacle You can't follow those instructions, it is possible
to flash U-Boot using serial console.
1. Insert FAT or EXT2/EXT3 formatted SD card with trimslice-spi.img,
2. Interrupt boot process to enter U-Boot command line,
3. Run following commands:
${fs}load mmc 0 0x04080000 trimslice-spi.img
sf probe 0
sf erase 0 0x100000
sf write 0x04080000 0x0 ${filesize}
reset
4. Poweroff, insert SD card with OpenWrt, boot and enjoy.
If something went wrong with one of above steps, there is simple
recovery option:
1. Open the µSD slot security door to access the recovery-boot button,
2. Insert SD card with OpenWrt to the front slot while unpowered,
3. Power on the TrimSlice while pressing the recovery-boot button,
4. With this it should boot straigth to OpenWrt, from there download
trimslice-spi.img and execute following commands:
mtd erase /dev/mtd0
mtd write trimslice-spi.img /dev/mtd0
5. Reboot, now it should boot straigth to OpenWrt, without pressing the
recovery-boot button, with proper U-Boot flashed.
Signed-off-by: Tomasz Maciej Nowak <tomek_n@o2.pl>
Add U-Boot for NVIDIA Tegra based boards, with the first being CompuLab
TrimSlice. This is part of initial support for this board.
Signed-off-by: Tomasz Maciej Nowak <tomek_n@o2.pl>
New target introduces initial support for NVIDIA Tegra SoC based devices.
It focuses on Tegra 2 CPUs, for successors supporting NEON instruction
set the target should be split in two subtargets.
This initial commit doesn't create any device image, it's groundwork
for further additions.
Signed-off-by: Tomasz Maciej Nowak <tomek_n@o2.pl>
It adjusts b53 code to upstream changes from the commit 3c1bcc8614db
("net: ethernet: Convert phydev advertize and supported from u32 to link
mode").
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Please note that modified code isn't currently being compiled with
kernels 4.19+ due to the dropped CONFIG_NF_CONNTRACK_IPV6 in upstream
Linux. That requires a separated fix.
This fixes:
net/netfilter/nf_conntrack_rtcache.c: In function 'nf_rtcache_get_cookie':
net/netfilter/nf_conntrack_rtcache.c:82:11: error: 'const struct rt6_info' has no member named 'rt6i_node'; did you mean 'rt6i_idev'?
if (rt->rt6i_node)
^~~~~~~~~
rt6i_idev
IPv6 structs were reworked in upstream kernel by:
commit a64efe142f5e ("net/ipv6: introduce fib6_info struct and helpers")
commit 77634cc67dc1 ("net/ipv6: Remove unused code and variables for rt6_info")
commit 93c2fb253d17 ("net/ipv6: Rename fib6_info struct elements")
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
This PR adds support for a popular low-cost 2.4GHz N based AP
Specifications:
- SoC: Qualcomm Atheros QCA9533 (650MHz)
- RAM: 64MB
- Storage: 8 MB SPI NOR
- Wireless: 2.4GHz N based built into SoC 2x2
- Ethernet: 1x 100/10 Mbps, integrated into SoC, 24V POE IN
Installation:
Flash factory image through stock firmware WEB UI
or through TFTP
To get to TFTP recovery just hold reset button while powering on
for around 4-5 seconds and release.
Rename factory image to recovery.bin
Stock TFTP server IP:192.168.0.100
Stock device TFTP adress:192.168.0.254
This is based on the support patch for the identical CPE210 v3
by Mario Schroen <m.schroen@web.de>.
Tested-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
[renamed dtsi filename]
Signed-off-by: Petr Štetiar <ynezz@true.cz>
Specifications:
* SoC: Qualcomm Atheros QCA9533 (650MHz)
* RAM: 64MB
* Storage: 8 MB SPI NOR
* Wireless: 2.4GHz N based built into SoC 2x2
* Ethernet: 1x 100/10 Mbps, integrated into SoC, 24V POE IN
Installation:
Flash factory image through stock firmware WEB UI or TFTP
To get to TFTP recovery just hold reset button while powering
on for around 4-5 seconds and release.
Rename factory image to recovery.bin
Stock TFTP server IP:192.168.0.100
Stock device TFTP adress:192.168.0.254
Thanks to robimarko for the work inside the ar71xx tree.
Thanks to adrianschmutzler for deep discussion and fixes.
Signed-off-by: Mario Schroen <m.schroen@web.de>
[Split into DTS/DTSI, read-only config partition in DTSI]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
[renamed dtsi filename, light subject touches]
Signed-off-by: Petr Štetiar <ynezz@true.cz>
Looks identical to the v2.
This PR adds support for a popular low-cost 2.4GHz N based AP
Specifications:
- SoC: Qualcomm Atheros QCA9533 (650MHz)
- RAM: 64MB
- Storage: 8 MB SPI NOR
- Wireless: 2.4GHz N based built into SoC 2x2
- Ethernet: 1x 100/10 Mbps, integrated into SoC, 24V POE IN
Installation:
Flash factory image through stock firmware WEB UI
or through TFTP
To get to TFTP recovery just hold reset button while powering on for
around 4-5 seconds and release.
Rename factory image to recovery.bin
Stock TFTP server IP:192.168.0.100
Stock device TFTP adress:192.168.0.254
Tested-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Signed-off-by: Robert Marko <robimarko@gmail.com>
[Rebased, adjusted for separate tplink-safeloader entry, dynamic partitioning]
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
This is also helpful to add support in ath79.
Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
Tested-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
I've missed leading whitespace issues in the original patch, so fixing
it in this commit. Thanks to pepe2k for letting me know.
Fixes: d260813d ("ar71xx: ens202ext: Fix VLAN switch")
Signed-off-by: Petr Štetiar <ynezz@true.cz>
This adds the SPDX license identifier for the NETGEAR EX6150. It was
missed when submitting the original patch.
Signed-off-by: David Bauer <mail@david-bauer.net>
The target ENS202EXT was just recently added right before the stable
release of Openwrt 18.
It flashes fine, but the physical switch is almost impossible to use
until you have a VLAN set up. Tested on two devices.
The actual problem is that eth0 represents nothing for whatever reason.
In other words, both WAN and LAN are running from eth1. There may be an
underlying problem in the build, but for now, I assume that this is
correct and that a VLAN switch is an appropriate fix.
Also, it's virtually impossible to get the switch running right through
LuCI. It is one thing to get a switch to appear, but attempting to
configure it breaks the whole thing. The VLAN has to be set up
perfectly, otherwise, interfaces will not start up, and one is forced to
reset settings, OR, the new LuCI feature kicks in and reverses any
steps. It is extremely difficult to determine which virtual ports
correspond to which physical ethernet ports without being able to set up
the switch in LuCI.
Temporary Workaround: followed directions here
[openwrt/luci#867](https://github.com/openwrt/luci/issues/867)
Reviewed-by: Marty Plummer <hanetzer@startmail.com>
Signed-off-by: Michael Pratt <mpratt51@gmail.com>
[commit author fix, subject fix, message text wrap]
Signed-off-by: Petr Štetiar <ynezz@true.cz>
The specific flash chip used (W25Q256FVEM) accepts 50MHz for read
requests and higher for others. 104MHz for fast reads. ramips seems to
be limited to 80MHz based on testing with higher values (no speedup).
Based on upstream commit: 97738374a310b9116f9c33832737e517226d3722
time dd if=/dev/mtdblock3 of=/dev/null bs=64k from 42.96s to 7.01s
[test done with backported upstream v4.19 driver[1], for numbers on
stock 4.14 driver please take a look at `ramips: Increase GB-PC2 SPI
frequency to 80MHz` commit message]
1. https://github.com/openwrt/openwrt/pull/1578
Signed-off-by: Rosen Penev <rosenp@gmail.com>
[expanded note about spi driver version]
Signed-off-by: Petr Štetiar <ynezz@true.cz>
The flash chip on the board (Spansion S25FL256SAIF00) is rated to
support at least 50MHz for normal read requests according to the
datasheet. 133MHz for fast reads. However, ramips seems to be limited to
80MHz.
>From testing this, higher values do not improve speeds.
time dd if=/dev/mtdblock3 of=/dev/null bs=64k from
42.82s to 14.09s.
boot speed is also faster:
[ 66.884087] procd: - init - vs
[ 48.976049] procd: - init -
Since spi speed was requested:
[ 3.538884] spi-mt7621 1e000b00.spi: sys_freq: 225000000
CPU is 900MHz:
[ 0.000000] CPU Clock: 900MHz
Signed-off-by: Rosen Penev <rosenp@gmail.com>
[fixed commit message by adding missing 0 in the spi-mt7621 clock output]
Signed-off-by: Petr Štetiar <ynezz@true.cz>
SoC: MediaTek MT7621
RAM: 64M (Winbond W9751G6KB-25)
FLASH: 16MB (Macronix MX25L12835F)
WiFi: MediaTek MT7662E bgn 2SS
WiFi: MediaTek MT7662E nac 2SS
BTN: ON/OFF - Reset - WPS - AP/Extender toggle
LED: - Arrow Right (blue)
- Arrow Left (blue)
- WiFi 1 (red/green)
- WiFi 2 (red/green)
- Power (green/amber)
- WPS (Green)
UART: UART is present as Pads on the backside of the PCB. They are
located on the other side of the Ethernet port.
3.3V - GND - TX - RX / 57600-8N1
3.3V is the nearest one to the antenna connectors
Installation
------------
Update the factory image via the Netgear web-interfaces (by default:
192.168.1.250/24).
You can also use the factory image with the nmrpflash tool.
For more information see https://github.com/jclehner/nmrpflash
Signed-off-by: David Bauer <mail@david-bauer.net>
[merge conflict in 02_network, flash@0 node rename, wlan DTS triggers]
Signed-off-by: Petr Štetiar <ynezz@true.cz>
Device specification:
- SoC: RT5350F
- CPU Frequency: 360 MHz
- Flash Chip: Winbond 25Q32 (4096 KiB)
- RAM: 32768 KiB
- 5x 10/100 Mbps Ethernet (4x LAN, 1x WAN)
- 1x external, non-detachable antenna
- UART (J1) header on PCB (57800 8n1)
- Wireless: SoC-intergated: 2.4GHz 802.11bgn
- USB: None
- 3x LED, 2x button
Flash instruction:
1. Configure PC with static IP 192.168.1.2/24 and start TFTP server.
2. Rename "openwrt-ramips-rt305x-kn_st-squashfs-sysupgrade.bin"
to "kstart_recovery.bin" and place it in TFTP server directory.
3. Connect PC with one of LAN ports, press the reset button, power up
the router and keep button pressed until power LED start blinking.
4. Router will download file from TFTP server, write it to flash and reboot.
Signed-off-by: Vladimir Kot <vova28rus@gmail.com>
[fixed git commit author and whitespace issues in DTS]
Signed-off-by: Petr Štetiar <ynezz@true.cz>
The WIZnet WizFi630S board is in the miniPCIe form factor.
SoC: Mediatek MT7688AN
RAM: 128MB
Flash: 32Mb
WiFi: 2.4GHz
Ethernet: 3x 100Mbit
USB: 1 (USB 2.0)
serial ports: 2 (1x full, 1xlite)
Flash and recovery instructions: Use the factory installed u-boot boot
loader. It is available on UART2 (115200,8,n,1). Then get the
sysupgrade image from a tftp server.
Signed-off-by: Tobias Welz <tw@wiznet.eu>
[whitespace and device name in makefile fixes]
Signed-off-by: Petr Štetiar <ynezz@true.cz>
This refreshes the current kernel configuration to remove unneeded
options, add some automatically added ones and reorders them. The normal
build did this automatically, so the builds already used this
configuration.
CONFIG_HW_RANDOM_OMAP is explicitly activated for the cortexa72
subtarget because it has an inside-secure,safexcel-eip76 IP core.
This was done with this command on the cortexa9 subtarget:
make kernel_oldconfig
and this one on the other subtargets:
make kernel_oldconfig CONFIG_TARGET=subtarget
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
This patch adds a ChromiumOS 3.18 patch [0] that fixes memory
allocation issues under memory pressure by keeping track
of missed allocs and rectify the omission at a later date.
It also adds ethtool counters for memory allocation
failures accounting so this can be verified.
[0] <d4e1e4ce68>
Reported-by: Chen Minqiang <ptpt52@gmail.com>
Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
Some broken ISPs (e.g. Comcast) send DHCPv6 packets with hop limit=0.
This trips up the TTL=0 check in the PPE if enabled.
Signed-off-by: Felix Fietkau <nbd@nbd.name>
COMFAST CF-E5/E7 is a outdoor 4G LTE AP with PoE support, based on
Qualcomm/Atheros QCA9531.
Short specification:
2x 10/100 Mbps Ethernet, with 24v PoE support
64 MB of RAM (DDR2)
16 MB of FLASH (SPI)
2T2R 2.4 GHz, 802.11b/g/n
built-in 1x 3 dBi antennas
output power (max): 80 mW (19 dBm)
Qucetel EC20 LTE MODULE(1x external detachable antenna)
Flash instruction:
Original firmware is based on OpenWrt.
Use sysupgrade image directly in vendor GUI.
Signed-off-by: Ding Tengfei <dtf@comfast.cn>
[commit subject fix]
Signed-off-by: Petr Štetiar <ynezz@true.cz>
This commit adds support for TP-Link TL-WR710N v1 router.
CPU: Atheros AR9331 400MHz
RAM: 32MB
FLASH: 8MiB
PORTS: 1 Port 100/10 LAN (connected to a switch), 1 Port 100/10 WAN
WiFi: Atheros AR9331 1x2:1 bgn
USB: ChipIdea HDRC USB2.0
LED: SYS
BTN: Reset
Sysupgrade from `ar71xx` works without glitches.
Network interfaces assigned for LAN and WAN ports are `eth1` and `eth0`
respectively, what's consistent with `ar71xx` target. Wireless radio
path is automatically upgraded from `platform/ar933x_wmac` to
`platform/ahb/18100000.wmac`.
Signed-off-by: Marcin Jurkowski <marcin1j@gmail.com>
This adds support for the Chinese version of TL-WR941N v7.
It uses QCA9558+AR8236 while the international version
uses TP9343 instead.
Specification:
- SoC: Qualcomm Atheros QCA9558
- Flash: 4 MB
- RAM: 64 MB
- Ethernet: Atheros AR8236 with 5 FE ports
Flash instruction:
Upload the generated factory firmware on web interface.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
This allows users to specify a shorter mib poll interval so that the
swconfig leds could behave normal with current get_port_stats()
implementation.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
This applies to ar8216 and ar8236. QCA's newer U-boot will enable
the switch mdio master for FE switches which makes phy inaccessible
from CPU mdio. (e.g. on TP-Link TL-WR941N v7 Chinese version which
uses QCA9558+AR8236.) For these devices PHY probing is broken and
mdio device probing is a must. We also need to disable switch mdio
master in driver for later PHY initialization.
Do a soft reset during hw_init so that mdio master can be disabled
and expose PHYs to CPU mdio for later PHY accessing.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
ar8xxx_mib_capture will update mib counters for all ports. Current
code only update one port at a time and the data for other ports
are lost.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Partially reverts commit eff3549c58.
AR7240 and AR9341 have buggy hardware switch LED trigger. The AR7240
one doesn't blink and the blinking of port0/port5 is reversed on
AR9341 if we swap PHY0 and PHY4. (Only blinking is reversed, which
means LED for PHY0 will lit when PHY0 is link up and will blink when
PHY4 has active link and vice versa.) On these two chips a software
swconfig LED trigger is required.
This commit adds swconfig port stats back but:
1. move checking of mib_t/rxb_id into ar8xxx_chip since we can't
distinguish ar7240sw and ar8216 using only chip id.
2. don't update mib counter in get_port_stat. This function is called
every 0.01s and this capturing procedure will take up a lot of CPU.
We already have a mib_work_func updating mib counters every 2s so
return the saved counter instead of fetching new data. The blinking
rate will be weird but it should solve the previously mentioned CPU
time problem.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
This builtin switch is a bugless ar8216 with different mib counters
and gigabit cpu port.
Atheros uses the same device ID and it's impossible to distinguish
the standalone one and the builtin one. So we add support to mdio
device probe only.
This switch doesn't have buggy vlan tag so it's not needed to enable
atheros header. This commit changed ar8216_setup_port so that it can
be reused for this switch.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
Atheros FE switches have a builtin mdio master available for PHY
accessing and on ar724x/ar933x builtin switches this mdio master
is the only way of accessing PHYs.
After this patch if there is phy_read/phy_write method available
in ar8xxx_chip we register a separated mdio bus for accessing PHYs.
Still adds support for mdio device probing only since this isn't
needed for those switches registered using PHY probing.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
ar8229 is the builtin switch in ar934x and later chips. There is
also a standalone version available and their registers/functions
are the same.
This commit added support for the builtin ar8229. The only thing
missing for standalone ar8229 should be phy modes. Since I don't
have a router using that, this commit doesn't add support for
other phy modes.
Only add its support for mdio-device probing method because the
current PHY probing can't return 1G speed when it's a FE switch.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
ar8xxx_id_chip is used to determine current ar8xxx_chip using switch
id and this isn't needed during mdiodev probing.
Move it out of ar8xxx_probe_switch so that we can skip it.
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
