Commit Graph

12 Commits

Author SHA1 Message Date
Adrian Schmutzler
7054721cf9 ath79: enable UART in SoC DTSI files
The uart node is enabled on all devices except one (GL-USB150 *).
Thus, let's not have a few hundred nodes to enable it, but do not
disable it in the first place.

Where the majority of devices is using it, also move the serial0
alias to the DTSI.

*) Since GL-USB150 even defines serial0 alias, the missing uart
   is probably just a mistake. Anyway, disable it for now so this
   patch stays cosmetic.

Apply this to 21.02 as well to remove an unnecessary backporting
pitfall.

Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
(cherry picked from commit 3a4b751110)
2021-02-25 14:42:11 +01:00
Adrian Schmutzler
3ca2d31c54 ath79: move ath79-clk.h include to ath79.dtsi
ath79.dtsi uses ATH79_CLK_MDIO, so the include

  <dt-bindings/clock/ath79-clk.h>

needs to be moved there.

Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
2020-09-25 23:24:09 +02:00
David Bauer
1f45ed6c99 ath79: fix QCA953x DDR and GPIO compatible bindings
The memory as well as GPIO controller had the wrong SoC name used for
their compatible binding.

Signed-off-by: David Bauer <mail@david-bauer.net>
2020-04-24 20:03:18 +02:00
David Bauer
d883eaacd4 ath79: add QCA9550 reset sequence
The QCA9550 family of SoCs have a slightly different reset
sequence compared to older chips.

Normally the bootloader performs this sequence, however
some bootloader implementation expect the operating system
to clear the reset. Also get the PCIe resets from OF to
support the second RC of the QCA9558.

This is required for the AVM FRITZ!WLAN Repeater 1750E to work,
as EVA leaves the PCIe bus in reset.

Tested: AVM FRITZ!WLAN Repeater 1750E - OCEDO Koala

Signed-off-by: David Bauer <mail@david-bauer.net>
2020-04-17 13:23:06 +02:00
Chuanhong Guo
ebf0d8dade ath79: add new ar934x spi driver
A new shift mode was introduced since ar934x which has a way better
performance than current bitbang driver and can handle higher spi
clock properly. This commit adds a new driver to make use of this
new feature.
This new driver has chipselect properly configured and we don't need
cs-gpios hack in dts anymore. Remove them.

Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
2020-02-06 22:53:03 +08:00
Adrian Schmutzler
6c407fb5db ath79: do not set inherited phy-mode/status properties again
There are several cases where phy-mode and status properties are
set again in DTS(I) files although those were set to the same values
in parent DTSI files already. Remove those cases (and thus also stop
their proliferation by copy/paste).

Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
2020-01-31 13:42:12 +01:00
Adrian Schmutzler
929becbc2d ath79: fix whitespace issues in DTS files
This is the result of grepping/searching for several common
whitespace issues like double empty lines, leading spaces, etc.

This patch fixes them for the ath79 target.

Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
2019-10-06 21:28:49 +02:00
Chuanhong Guo
f65501e1c2 ath79: ar93xx/qca95xx: move gmac/wmac/pcie node out of apb bus
according to functional block diagram in datasheet, these devices
don't belong to apb bus.
Move these nodes out to match datasheet description.

Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
2019-07-16 09:52:43 +08:00
Chuanhong Guo
8dde11d521 ath79: dts: drop "simple-mfd" for gmacs in SoC dtsi
With a proper probe deferring for ag71xx we don't need to explicitly
probe mdio1 before gmac0.
Drop all "simple-mfd" in SoC dtsi so that gmac orders can be the same
as ar71xx.
This makes eth0/eth1 order the same as those in ar71xx, which means
we don't need a migration script for this anymore and we can merge
incorrectly split gmac/mdio driver back together.

Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
2019-06-05 10:12:31 +02:00
Chuanhong Guo
443fc9ac35 ath79: use ar8216 for builtin switch
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
2019-03-24 01:44:27 +01:00
Chuanhong Guo
3bd871ad52 ath79: fix wmac memory region for qca953x
According to /arch/mips/include/asm/mach-ath79/ar71xx_regs.h
the size of wmac register range for qca953x is only 0x20000.

Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
2019-02-20 18:51:31 +01:00
Chuanhong Guo
c36ec336a3 ath79: rename qca9533.dtsi to qca953x.dtsi
qca9533 is a costdown version of qca9531 which doesn't have USB and PCIE.
Rename the misleading dtsi names and fix the SoC type of gl-ar300m.

Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
[apply the changes for the gl-x750 as well]
Signed-off-by: Mathias Kresin <dev@kresin.me>
2018-12-06 12:17:25 +01:00