Hardware specification
----------------------
* RTL8380M SoC, 1 MIPS 4KEc core @ 500MHz
* 256MB DRAM
* 32MB NOR Flash
* 8 x 10/100/1000BASE-T ports
* 2 x SFP ports
* Power LED, Fault LED
* Reset button on front panel
* UART (115200 8N1) via populated standard pin header marked JP1
TODO: The SFP ports use a shared SCL GPIO that the driver cannot handle.
The left SFP port (lan9) is defined and fully functional while the laser
on the right SFP port (lan10) is off by default.
UART pinout
-----------
[o]ooo|JP1
| ||`------ GND
| |`------- RX
| `-------- TX
`---------- Vcc (3V3)
Installation using OEM webinterface
-----------------------------------
1. Make sure you are running OEM firmware in secondary slot
2. Install squashfs-factory.imag to primary slot by upload via http
Installation using serial interface
-----------------------------------
1. Press "a" "c" "p" during message "Enter correct key to stop autoboot"
2. Load image with "upgrade runtime <TFTP IP>:squashfs-sysupgrade.bin" command
3. Switch to primary slot with "setsys bootpartition 0"
4. Store config with "savesys"
5. Boot the image with `boota` command
Dual-boot with stock firmware using writable u-boot-env
-------------------------------------------------------
From stock to OpenWrt / primary image 1 (CLI as admin):
- > boot system image1
- > reboot
From OpenWrt to stock / boot image 2: (shell as root)
- # fw_setsys bootpartition 1
- # reboot
Debrick using serial interface
------------------------------
1. Press "a" "c" "p" during message "Enter correct key to stop autoboot"
2. Load vendor image with "upgrade runtime <TFTP IP>:LGS310xxxxx.imag"
3. switch to primary partition "setsys bootpartition 0"
4. safe config "savesys"
Further documentation
---------------------
See https://openwrt.org/toh/linksys/lgs352c
It has been developed and tested on device with v1 revision.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/16068
[Add missing 'w' in name of firmware partition]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
General hardware info:
----------------------
D-Link DGS-1210-28P rev. F1 is a switch with 24 ethernet ports and 4
combo ports, all ports Gbit capable. It is based on a RTL8382 SoC
@500MHz, DRAM 128MB and 32MB flash. 24 ethernet ports are 802.3af/at PoE
capable with a total PoE power budget of 193W.
Power over Ethernet:
--------------------
The PSE hardware consists of three BCM59121 PSE chips, serving 8 ports
each. They are controlled by a Nuvoton MCU. In order to enable PoE, the
realtek-poe package is required. It is installed by default, but
currently it requires the manual editing of /etc/config/poe. Keep in
mind that the port number assignment does not match on this switch,
alway 8 ports are in reversed order: 8-1, 16-9 and 24-17.
LEDs and Buttons:
-----------------
On stock firmware, the mode button is supposed to switch the LED
indicators of all port LEDs between Link Activity and PoE status. The
currently selected mode is visualized using the respective LEDs. PoE Max
indicates that the maximum PoE budget has been reached. Since there is
currently no support for this behavior, these LEDs and the mode button
can be used independently.
Serial connection:
------------------
The UART for the SoC (115200 8N1) is available via unpopulated standard
0.1" pin header marked J6. Pin1 is marked with arrow and square.
Pin 1: Vcc 3.3V
Pin 2: Tx
Pin 3: Rx
Pin 4: Gnd
OEM installation from Web Interface:
------------------------------------
1. Make sure you are booting using OEM in image 2 slot. If not,
switch to
image2 using the menus
System > Firmware Information > Boot from image2
Tools > reboot
2. Upload image in vendor firmware via Tools > Backup / Upgrade
Firmware > image1
3. Toggle startup image via System > Firmware Information > Boot
from
image1
4. Tools > reboot
Other installation methods not tested, but since the device shares the
board with the DGS-1210-28, the following should work:
Boot initramfs image from U-Boot:
---------------------------------
1. Press Escape key during `Hit Esc key to stop autoboot` prompt
2. Press CTRL+C keys to get into real U-Boot prompt
3. Init network with `rtk network on` command
4. Load image with `tftpboot 0x8f000000
openwrt-rtl838x-generic-d-link_dgs-1210-28p-f-initramfs-kernel.bin`
command
5. Boot the image with `bootm` command
Signed-off-by: Luiz Angelo Daros de Luca <luizluca@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/15938
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Drop config and files for Linux 5.15.
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
Link: https://github.com/openwrt/openwrt/pull/16417
Signed-off-by: Robert Marko <robimarko@gmail.com>
Hardware information:
---------------------
- SoC: RTL8393M
- Copper phy: 6×RTL8218B
- Fibre phy: RTL8214FC
- Flash: 32MiB SPI NOR, MX25L25635FMI
- RAM: 128MiB DDR3, Micron MT41K64M16TW-107
- Serial port: ±5V serial port to RJ45, ZT3232 (MAX3232 compatible)
- +370W POE on JG928A model
Note: SFP ports currently non-functional due to missing support for
RTL8214FC on the RTL8393M target.
Updated for Linux 6.6 kernel.
Installation:
-------------
- Initial installation follows same process as HPE 1920-24G (JG924A)
- Based on prior work of Jan Hoffmann <jan@3e8.eu>
- Additional work by Andreas Böhler <dev@aboehler.at>
- PoE updates and tidy-up by Stephen Howell <howels@allthatwemight.be>
Signed-off-by: Stephen Howell <howels@allthatwemight.be>
Now that there is 6.6 support for realtek, lets encourage testing it by
making it default so 5.15 can be dropped ASAP.
Link: https://github.com/openwrt/openwrt/pull/16408
Signed-off-by: Robert Marko <robimarko@gmail.com>
Merging of the realtek 6.6 series forgot to include some final fixes
for the new MDIO driver. What was changed in last second?
1. The MDIO driver used wrong constants to make use of the raw
page (for direct register access). Provide a rawpage variable in
the bus private structure, populate it during initialization and
make use of it at the proper places
2. We always used the variable portaddr for the bus index. Usually
our driver uses either addr or port for the same meaning. Remove the
duplication and reuse the normal addr variable.
3. Drop functions rtmdio_write_page() and rtmdio_read_page(). These
only call the PHY driver read/write page functions. We know that
these will only access page 0x1f. As we have only Realtek PHYs
and our driver only reacts to this special page, just hardcode it.
Benefit is that we can use these functions for PHY detection when
read/write page functions are not yet assigned.
4. Add two new helper functions phy_port_read_paged() and
phy_port_write_paged(). These allow to access arbitrary ports on
the MDIO bus when the packages are not initialized. These will be
needed for proper RTL8218B and RTL8214FC detection in forthcoming
patches.
5. The port tracking wrongly used index 0 to mark "normal" access.
This does not allow to make a "special" access to port 0. Use
index -1 to mark "normal" access.
Provide the fix for 5.15 and 6.6 to allow for easy version
comparison.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/16391
Signed-off-by: Robert Marko <robimarko@gmail.com>
With commit a22d359fa5 VLAN handling was fixed for kernel 6.6.
This restored network connectivity of the devices. For easy testing
backport the fix for 5.15 too.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/16391
Signed-off-by: Robert Marko <robimarko@gmail.com>
On the XGS1210-12 the RTL8218D is attached via XGMII. Add this to the
supported list in the DSA driver.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/16391
Signed-off-by: Robert Marko <robimarko@gmail.com>
The DGS-1210-28MP has a LM63 fan controller connected via i2c of the
RTL8231. The clock line is always low if the property
i2c-gpio,scl-open-drain is not set; with this property, the GPIO pin is
force-drive and the clock works as expected.
The LM63 is not configured by U-Boot, thus only manual fan control is
possible by settings pwm1_enable to "1" and writing the desired values to
pwm1.
The OEM firmware drives the fan from user mode and sets it up like this:
// PWM LUT/value r/w, PWM Clock = 1.4kHz
0x4a 0x28
// Tachometer spinup disabled, spin-up cycles bypassed
0x4b 0x00
// PWM Frequency = default
0x4d 0x17
// PWM Value (28)
0x4c 0x1c
// If > 0 C, use
0x50 0x00
// PWM = 28
0x51 0x1c
// If > 51 C, use
0x52 0x33
// PWM = 44
0x53 0x2e
// Set hysteresis to 100 = default
0x4f 0x03
// Turn on automatic mode and w/p the LUT values
0x4a 0x08
A thread in the OEM firmware polls the ALERT status register for fan
failures.
Unfortunately, the lm63 kernel driver does not perform any initialization
of the chip and it does not support changing some config registers (like
PWM frequency or LUT). Hence, we are stuck with the defaults and need to do
fan control in software.
Signed-off-by: Andreas Böhler <dev@aboehler.at>
Link: https://github.com/openwrt/openwrt/pull/15616
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The DGS-1210-28 series was lacking full SFP support due to missing GPIOs.
Fortunately, the existing GPIO definitions of DGS-1210-52 match, this adds
the required i2c-gpio nodes to the DTS and allows hotplug SFP support.
Signed-off-by: Andreas Böhler <dev@aboehler.at>
Link: https://github.com/openwrt/openwrt/pull/15616
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The CPU port of realtek switches needs some proper PVID set to handle
untagged packets. Because the ethernet driver does no special VLAN
handling (see CPU tag RVID/RVID_SEL) as of now we can only steer
untagged packets by setting PVID for the CPU port. VLAN handling has
never been perfect but 3 events made things worse.
- Commit a376508216 ("rtl83xx: dsa: Do nothing when vid 0")
- Commit e691e2b302 ("rtl83xx: dsa: reset PVID to 1 instead of 0")
- Upgrade to kernel 6.6
Reasons are:
- Rejecting VID 0 disabled Linux initialization routines
- Initialization for PVID forgot to set priv->ports[port].pvid
- Kernel 6.6 does no longer clarify CPU port as untagged
To fix this prepare the VID 0 setup inside the driver. Join all ports
to VID 0 and let no one from outsinde interfere with this setup.
Especially ignore PVID settings for the CPU port for all further
VLAN commands.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Suggested-by: Bjørn Mork <bjorn@mork.no>
Since kernel commit c5714f68a76bcad3d ("net: phylink: explicitly invalidate
link_state members in mac_config") it should be clear that link data can
only be used in mac_link_up(). Refactor that for the RTL83xx targets.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Some devices (e.g. HP JG924A) hand over other than expected kernel boot
arguments. Looking at these one can see:
fw_init_cmdline: fw_arg0=00020000
fw_init_cmdline: fw_arg1=00060000
fw_init_cmdline: fw_arg2=fffdffff
fw_init_cmdline: fw_arg3=0000416c
Especially fw_arg2 should be the pointer to the environment and it looks
very suspicous. It is not aligned and the address is outside KSEG0 and
KSEG1. Booting the device will result in a hang. Do better at verifying
the address.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Suggested-by: Bjørn Mork <bjorn@mork.no>
The supported_interfaces bitmap cannot be empty since mainline kernel
commit de5c9bf40c45 ("net: phylink: require supported_interfaces to
be filled"). Fix the dsa and ethernet driver accordingly.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
The DSA framework has changed a bit since 6.1, lets adapt to match.
Currently there is no one-patch-fits-all solution to directly fix
all errors up to 6.6. So cover the final differences with this
second patch.
Most notable upstream changes are:
- a88dd7538461 ("net: dsa: remove legacy_pre_march2020 detection")
- 53d04b981110 ("net: dsa: remove phylink_validate() method")
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[Minor checkpatch.pl cleanups]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
The DSA framework has changed a bit since 5.15, lets adapt to match.
Currently there is no one-patch-fits-all solution to directly fix
all errors up to 6.6. So at least take all the already known changes
that cover differences between 5.15 and 6.1
Most notable upstream changes are:
- d3eed0e57d5d ("net: dsa: keep the bridge_dev and bridge_num as part
of the same structure")
Update of port_bridge_{join,leave}: use same helper as upstream
- c26933639b54 ("net: dsa: request drivers to perform FDB isolation")
Update of port_fdb_{add,del}, port_mdb_{add,del}
- dedd6a009f41 ("net: dsa: create a dsa_lag structure")
Update of port_lag_{join,leave}
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
[align updates with upstream, add references to upstream commits]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
No content changes. Only take over the new patch locations. All errors
that wil arise from compiling with the phy driver will be covered by
follow up patches.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
No content changes. Only adapt the failing hooks and take over the
new patch locations. All errors that wil arise from compiling with
the dsa driver will be covered by follow up patches.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
A lot of stuff has been converted to the phylink_pcs_ops structure.
Adapt the ethernet driver to make use of it.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
We no longer are required to pass the weight to netif_napi_add.
See commit b48b89f9c189 ("net: drop the weight argument from netif_napi_add").
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
This is not a surprise. Before upgrade to 6.6 we refactored the mdio part of
the ethernet driver and knew that changes will come. Drop all unnecessary
stuff from the old world and adapt to the new kernel.
- remove legacy functions
- directly link new functions
- adapt to new shared base address
- remove references to old MDIO bus capabilities
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
No content changes. Only take over the new patch locations. All errors
that will arise from compiling with the ethernet driver will be covered
by follow up patches.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
With the new kernel the MDIO bus gets created after the smbus
read/write functions are used. Make use of native functions.
Relocate bus initialization into a separate function to make
patch easier to read.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Take over the new patch locations and add references to the link mode into
phylink_sfp_interface_preference[] and phylink_get_capabilities().
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
No content changes. As the order of the 7xx patch files seems very
strange reorder all of them according to the realtek 6.6 kernel upgrade
effort.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
No content changes. Only take over the new patch locations.
With this patch all platform specific changes for kernel 6.6 are in place.
Realtek devices are bootable from serial console. VPE is fully functional
on devices that support it. The switch functions (ethernet and DSA) are
not enabled yet.
Boot tested on RTL8380 (Linksys LGS310C) and RTL8393 (Zyxel GS1920-24).
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
