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realtek: 6.6: refactor mac config and link up for RTL83xx
Since kernel commit c5714f68a76bcad3d ("net: phylink: explicitly invalidate
link_state members in mac_config") it should be clear that link data can
only be used in mac_link_up(). Refactor that for the RTL83xx targets.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
This commit is contained in:
Markus Stockhausen
Sander Vanheule
parent
dc9fca1fd1
commit
cd958d945b
@ -671,104 +671,31 @@ static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
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unsigned int mode,
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const struct phylink_link_state *state)
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{
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struct dsa_port *dp = dsa_to_port(ds, port);
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struct rtl838x_switch_priv *priv = ds->priv;
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u32 reg;
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int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;
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u32 mcr;
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pr_debug("%s port %d, mode %x\n", __func__, port, mode);
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if (port == priv->cpu_port) {
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/* Set Speed, duplex, flow control
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* FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
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* | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
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* | MEDIA_SEL
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*/
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if (priv->family_id == RTL8380_FAMILY_ID) {
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sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
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/* allow CRC errors on CPU-port */
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sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
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} else {
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sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
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}
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/* currently only needed for RTL8380 */
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if (priv->family_id != RTL8380_FAMILY_ID)
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return;
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if (dsa_port_is_cpu(dp)) {
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/* allow CRC errors on CPU-port */
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sw_w32_mask(0, 0x8, priv->r->mac_port_ctrl(port));
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return;
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}
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reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
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/* Auto-Negotiation does not work for MAC in RTL8390 */
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if (priv->family_id == RTL8380_FAMILY_ID) {
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if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) {
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pr_debug("PHY autonegotiates\n");
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reg |= RTL838X_NWAY_EN;
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sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
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rtl83xx_config_interface(port, state->interface);
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return;
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}
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mcr = sw_r32(priv->r->mac_force_mode_ctrl(port));
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if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) {
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pr_debug("port %d PHY autonegotiates\n", port);
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rtl83xx_config_interface(port, state->interface);
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mcr |= RTL838X_NWAY_EN;
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} else {
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mcr &= ~RTL838X_NWAY_EN;
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}
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if (mode != MLO_AN_FIXED)
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pr_debug("Fixed state.\n");
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/* Clear id_mode_dis bit, and the existing port mode, let
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* RGMII_MODE_EN bet set by mac_link_{up,down} */
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if (priv->family_id == RTL8380_FAMILY_ID) {
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reg &= ~(RTL838X_RX_PAUSE_EN | RTL838X_TX_PAUSE_EN);
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if (state->pause & MLO_PAUSE_TXRX_MASK) {
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if (state->pause & MLO_PAUSE_TX)
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reg |= RTL838X_TX_PAUSE_EN;
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reg |= RTL838X_RX_PAUSE_EN;
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}
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} else if (priv->family_id == RTL8390_FAMILY_ID) {
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reg &= ~(RTL839X_RX_PAUSE_EN | RTL839X_TX_PAUSE_EN);
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if (state->pause & MLO_PAUSE_TXRX_MASK) {
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if (state->pause & MLO_PAUSE_TX)
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reg |= RTL839X_TX_PAUSE_EN;
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reg |= RTL839X_RX_PAUSE_EN;
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}
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}
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reg &= ~(3 << speed_bit);
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switch (state->speed) {
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case SPEED_1000:
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reg |= 2 << speed_bit;
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break;
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case SPEED_100:
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reg |= 1 << speed_bit;
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break;
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default:
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break; /* Ignore, including 10MBit which has a speed value of 0 */
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}
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if (priv->family_id == RTL8380_FAMILY_ID) {
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reg &= ~(RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
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if (state->link)
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reg |= RTL838X_FORCE_LINK_EN;
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if (state->duplex == RTL838X_DUPLEX_MODE)
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reg |= RTL838X_DUPLEX_MODE;
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} else if (priv->family_id == RTL8390_FAMILY_ID) {
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reg &= ~(RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
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if (state->link)
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reg |= RTL839X_FORCE_LINK_EN;
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if (state->duplex == RTL839X_DUPLEX_MODE)
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reg |= RTL839X_DUPLEX_MODE;
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}
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/* LAG members must use DUPLEX and we need to enable the link */
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if (priv->lagmembers & BIT_ULL(port)) {
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switch(priv->family_id) {
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case RTL8380_FAMILY_ID:
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reg |= (RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
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break;
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case RTL8390_FAMILY_ID:
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reg |= (RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
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break;
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}
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}
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/* Disable AN */
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if (priv->family_id == RTL8380_FAMILY_ID)
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reg &= ~RTL838X_NWAY_EN;
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sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
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sw_w32(mcr, priv->r->mac_force_mode_ctrl(port));
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}
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static void rtl931x_phylink_mac_config(struct dsa_switch *ds, int port,
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@ -916,12 +843,14 @@ static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
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phy_interface_t interface)
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{
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struct rtl838x_switch_priv *priv = ds->priv;
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int mask = 0;
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/* Stop TX/RX to port */
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sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
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/* No longer force link */
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sw_w32_mask(0x3, 0, priv->r->mac_force_mode_ctrl(port));
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mask = RTL83XX_FORCE_EN | RTL83XX_FORCE_LINK_EN;
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sw_w32_mask(mask, 0, priv->r->mac_force_mode_ctrl(port));
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}
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static void rtl93xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
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@ -949,10 +878,60 @@ static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
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int speed, int duplex,
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bool tx_pause, bool rx_pause)
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{
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struct dsa_port *dp = dsa_to_port(ds, port);
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struct rtl838x_switch_priv *priv = ds->priv;
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u32 mcr, spdsel;
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if (speed == SPEED_1000)
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spdsel = RTL_SPEED_1000;
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else if (speed == SPEED_100)
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spdsel = RTL_SPEED_100;
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else
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spdsel = RTL_SPEED_10;
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mcr = sw_r32(priv->r->mac_force_mode_ctrl(port));
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if (priv->family_id == RTL8380_FAMILY_ID) {
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mcr &= ~RTL838X_RX_PAUSE_EN;
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mcr &= ~RTL838X_TX_PAUSE_EN;
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mcr &= ~RTL838X_DUPLEX_MODE;
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mcr &= ~RTL838X_SPEED_MASK;
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mcr |= RTL83XX_FORCE_LINK_EN;
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mcr |= spdsel << RTL838X_SPEED_SHIFT;
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if (tx_pause)
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mcr |= RTL838X_TX_PAUSE_EN;
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if (rx_pause)
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mcr |= RTL838X_RX_PAUSE_EN;
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if (duplex == DUPLEX_FULL || priv->lagmembers & BIT_ULL(port))
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mcr |= RTL838X_DUPLEX_MODE;
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if (dsa_port_is_cpu(dp))
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mcr |= RTL83XX_FORCE_EN;
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} else if (priv->family_id == RTL8390_FAMILY_ID) {
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mcr &= ~RTL839X_RX_PAUSE_EN;
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mcr &= ~RTL839X_TX_PAUSE_EN;
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mcr &= ~RTL839X_DUPLEX_MODE;
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mcr &= ~RTL839X_SPEED_MASK;
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mcr |= RTL83XX_FORCE_LINK_EN;
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mcr |= spdsel << RTL839X_SPEED_SHIFT;
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if (tx_pause)
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mcr |= RTL839X_TX_PAUSE_EN;
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if (rx_pause)
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mcr |= RTL839X_RX_PAUSE_EN;
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if (duplex == DUPLEX_FULL || priv->lagmembers & BIT_ULL(port))
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mcr |= RTL839X_DUPLEX_MODE;
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if (dsa_port_is_cpu(dp))
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mcr |= RTL83XX_FORCE_EN;
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}
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pr_debug("%s port %d, mode %x, speed %d, duplex %d, txpause %d, rxpause %d: set mcr=%08x\n",
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__func__, port, mode, speed, duplex, tx_pause, rx_pause, mcr);
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sw_w32(mcr, priv->r->mac_force_mode_ctrl(port));
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/* Restart TX/RX to port */
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sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
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/* TODO: Set speed/duplex/pauses */
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}
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static void rtl93xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
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@ -144,17 +144,24 @@
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#define RTL931X_MAC_LINK_MEDIA_STS (0x0EC8)
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/* MAC link state bits */
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#define RTL838X_FORCE_EN (1 << 0)
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#define RTL838X_FORCE_LINK_EN (1 << 1)
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#define RTL_SPEED_10 0
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#define RTL_SPEED_100 1
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#define RTL_SPEED_1000 2
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#define RTL83XX_FORCE_EN (1 << 0)
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#define RTL83XX_FORCE_LINK_EN (1 << 1)
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#define RTL838X_NWAY_EN (1 << 2)
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#define RTL838X_DUPLEX_MODE (1 << 3)
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#define RTL838X_SPEED_SHIFT (4)
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#define RTL838X_SPEED_MASK (3 << RTL838X_SPEED_SHIFT)
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#define RTL838X_TX_PAUSE_EN (1 << 6)
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#define RTL838X_RX_PAUSE_EN (1 << 7)
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#define RTL838X_MAC_FORCE_FC_EN (1 << 8)
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#define RTL839X_FORCE_EN (1 << 0)
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#define RTL839X_FORCE_LINK_EN (1 << 1)
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#define RTL839X_DUPLEX_MODE (1 << 2)
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#define RTL839X_SPEED_SHIFT (3)
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#define RTL839X_SPEED_MASK (3 << RTL839X_SPEED_SHIFT)
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#define RTL839X_TX_PAUSE_EN (1 << 5)
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#define RTL839X_RX_PAUSE_EN (1 << 6)
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#define RTL839X_MAC_FORCE_FC_EN (1 << 7)
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