Adjusting dts will cause a rebuild of whole kernel as the buildroot
considers this a part of kernel source. It's a royal PITA when trying to
prepare support for new device, since this takes a lot of time on slower
systems. As it stands, buildroot itself, with own rule, also compiles
dtbs and the results are $(KDIR)/image-$(DEVICE_DTS).dtb. With setting
DEVICE_DTS_DIR to directory holding the device dts (similarly to some
other targets), buildroot doesn't consider changed dts as part of kernel
source and rebuilds only dtb. This really speeds up development. And
since the kernel built dts are no longer used, drop the paches adding
dtses to its build.
Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com>
Reviewed-by: Robert Marko <robimarko@gmail.com>
Import patches from Linux v5.16 and v5.17 to get 2500Base-X SFP working
again with mvneta driver after the generic phylink validate backport.
Fixes: aab466f422 ("kernel: backport generic phylink validate")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Airoha is a new ARM platform based on Cortex-A53 which has recently been
merged into linux-next.
Due to BootROM limitations on this platform, the Cortex-A53 can't run in
Aarch64 mode and code must be compiled for 32-Bit ARM.
This support is based mostly on those linux-next commits backported
for kernel 5.15.
Patches:
1 - platform support = linux-next
2 - clock driver = linux-next
3 - gpio driver = linux-next
4 - linux,usable-memory-range dts support = linux-next
5 - mtd spinand driver
6 - spi driver
7 - pci driver (kconfig only, uses mediatek PCI) = linux-next
Still missing:
- Ethernet driver
- Sysupgrade support
A.t.m there exists one subtarget EN7523 with only one evaluation
board.
The initramfs can be run with the following commands from u-boot:
-
u-boot> setenv bootfile \
openwrt-airoha-airoha_en7523-evb-initramfs-kernel.bin
u-boot> tftpboot
u-boot> bootm 0x81800000
-
Signed-off-by: Daniel Danzberger <daniel@dd-wrt.com>
8 and 16 bit writes to the GPIO peripheral are apparently not supported,
and only worked most of the time. This resulted in garbabe writes to the
interrupt mask registers, causing spurious unhandled interrupts, which
could lead to CPU lock-ups as these kept retriggering.
Instead of clearing these spurious interrupt when they occur, the
upstream patch will just make sure all register writes have the intended
result, so these don't happen at all.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Make sure the compatible string in DTS matches the now v1/v2
differentiated board name in target/linux/mediatek/image/mt7622.mk.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
As of upstream Linux commit 0fe1e96fef0a ("powerpc/pci: Prefer PCI
domain assignment via DT 'linux,pci-domain' and alias"), the PCIe
domain address is no longer numbered by the lowest 16 bits of the PCI
register address after a fallthrough. Instead of the fallthrough, the
enumeration process accepts the alias ID (as determined by
`of_alias_scan()`). This causes e.g.:
9000:00:00.0 PCI bridge: Freescale Semiconductor Inc P1020E (rev 11)
9000:01:00.0 Network controller: Qualcomm Atheros AR958x 802.11abgn ...
to become
0000:00:00.0 PCI bridge: Freescale Semiconductor Inc P1020E (rev 11)
0000:01:00.0 Network controller: Qualcomm Atheros AR958x 802.11abgn ...
... which then causes the sysfs path of the netdev to change,
invalidating the `wifi_device.path`s enumerated in
`/etc/config/wireless`.
One other solution might be to migrate the uci configuration, as was
done for mvebu in commit 0bd5aa89fc ("mvebu: Migrate uci config to
new PCIe path"). However, there are concerns that the sysfs path will
change once again once some upstream patches[^2][^3] are merged and
backported (and `CONFIG_PPC_PCI_BUS_NUM_DOMAIN_DEPENDENT` is enabled).
Instead, remove the aliases and allow the fallthrough to continue for
now. We will provide a migration in a later release.
This was first reported as a Github issue[^1].
[^1]: https://github.com/openwrt/openwrt/issues/10530
[^2]: https://lore.kernel.org/linuxppc-dev/20220706104308.5390-1-pali@kernel.org/t/#u
[^3]: https://lore.kernel.org/linuxppc-dev/20220706101043.4867-1-pali@kernel.org/Fixes: #10530
Tested-by: Martin Kennedy <hurricos@gmail.com>
[Tested on the Aerohive HiveAP 330 and Extreme Networks WS-AP3825i]
Signed-off-by: Martin Kennedy <hurricos@gmail.com>
Commit 0b7c66c ("at91bootstrap: add sama5d27_som1_eksd1_uboot as
default defconfig") changed default booting media for sama5d27_som1_ek
board w/o any reason. Changed it back to sdmmc0 as it is for all the
other Microchip supported distributions for this board (Buildroot,
Yocto Project). The initial commit cannot be cleanly reverted.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Commit adc69fe (""uboot-at91: changed som1 ek default defconfigs")
changed the booting media to sdmmc1 as default booting w/o any reason.
The Microchip releases for the rest of supported distributions (Buildroot,
Yocto Project) uses sdmmc0 as default booting media for this board.
Thus change it back to sdmmc0. With this remove references to sdmmc1
config. The initial commit cannot be cleanly reverted.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Backport commit from Linux 5.18 fixing phylink with DSA drivers which
do not provide mac_select_pcs yet.
Fixes: aab466f422 ("kernel: backport generic phylink validate")
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Since introduction of clock driver we have a new kernel config
setting. Provide an initial value for the 930x targets.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Some devices have wrong/empty values in the PLL registers. Work
around that by reporting the default values.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
The Bananapi BPi-R3 is a development router board built around the
MediaTek Filogic 830 (MT7986A) SoC.
The board can boot either from microSD, SPI-NAND, SPI-NOR or eMMC.
Only either SPI-NAND or SPI-NOR can be used at the same time, also only
either microSD or eMMC can be used. The various storage options can be
selected using small SMD switches on the board.
Specs:
* MediaTek MT7986A (Filogic 830) 4x ARM Cortex A53
* 4T4R 2.4G 802.11bgnax (MT7975N)
* 4T4R 5G 802.11anac/ax (MT7975P)
* 2 GB DDR4 RAM
* 8 GB eMMC
* 128 MB SPI-NAND flash
* 32 MB SPI-NOR flash
* on-board MT7531 GbE switch
* 2x SFP+ (1 GbE / 2.5 GbE)
* 5x GbE network port
* miniPCIe slot (only USB 2.0 connected)
* uSIM slot (connected to miniPCIe interface)
* M.2 KEY-E PCIe interface (PCIe x2)
* microSD card interface
* 26 PIN GPIO
Hardware details: https://wiki.banana-pi.org/Banana_Pi_BPI-R3
Working:
* all 4 boot methods incl. installation via U-Boot, sysupgrade, ...
* copper LAN and WAN ports
* SFP1 (connected to gmac1, eth1 in Linux)
* WiFi
* LEDs
* Buttons
* PSTORE/ramoops based dual-boot
Not Working (missing driver features):
* SFP2 (connected to MT7531 switch)
Untested:
* M.2/NGFF slot (PCIe x2)
* mPCIe slot (USB 2.0 + SIM)
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Backport generic phylink validate series and make use of it for
mtk_eth_soc Ethernet driver as well as mt7530 DSA driver.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
This patch defines the two switch LED to bring them under user control.
Fixes: a0e1d3ab7b ("ramips: improve YunCore AX820 LEDs")
Signed-off-by: Thibaut VARÈNE <hacks@slashdirt.org>
[rmilecki: leave "label"s in place]
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
The SG2008P has its ethernet ports in the rear, and LEDs in the front.
The ports should be labeled lan8->lan1, not lan1->lan8. To resolve
this, fix the phy mapping in the "ports" node.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Address 0x30 is a "broadcast" address for the TPS23861. It should not
be used by drivers, as all TPS23861 devices on the bus are supposed to
respond. Change this to the correct address, 0x28.
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
When marking a switch port as disabled in the device tree, by using
'status = "disabled";', the switch driver fails on boot, causing a
restart:
CPU 0 Unable to handle kernel paging request at virtual address
00000000, epc == 802c3064, ra == 8022b4b4
[ ... ]
Call Trace:
[<802c3064>] strlen+0x0/0x2c
[<8022b4b4>] start_creating.part.0+0x78/0x194
[<8022bd3c>] debugfs_create_dir+0x44/0x1c0
[<80396dfc>] rtl838x_dbgfs_port_init+0x54/0x258
[<80397508>] rtl838x_dbgfs_init+0xe0/0x56c
This is caused by the DSA subsystem (mostly) ignoring the port, while
rtl83xx_mdio_probe() still extracts some details on this disabled port
from the device tree, resulting in the usage of a NULL pointer where a
port name is expected.
By not probing ignoring disabled ports, no attempt is made to create a
debugfs directory later. The device then boots as expected without the
disabled port.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Specifications:
- SoC: Qualcomm Atheros QCA9557-AT4A
- RAM: 2x 128MB Nanya NT5TU64M16HG
- FLASH: 64MB - SPANSION FL512SAIFG1
- LAN: Atheros AR8035-A (RGMII GbE with PoE+ IN)
- WLAN2: Qualcomm Atheros QCA9557 2x2 2T2R
- WLAN5: Qualcomm Atheros QCA9882-BR4A 2x2 2T2R
- SERIAL: UART pins at J10 (115200 8n1)
Pinout is 3.3V - GND - TX - RX (Arrow Pad is 3.3V)
- LEDs: Power (Green/Amber)
WiFi 5 (Green)
WiFi 2 (Green)
- BTN: Reset
Installation:
1. Download the OpenWrt initramfs-image.
Place it into a TFTP server root directory and rename it to 1D01A8C0.img
Configure the TFTP server to listen at 192.168.1.66/24.
2. Connect the TFTP server to the access point.
3. Connect to the serial console of the access point.
Attach power and interrupt the boot procedure when prompted.
Credentials are admin / new2day
4. Configure U-Boot for booting OpenWrt from ram and flash:
$ setenv boot_openwrt 'setenv bootargs; bootm 0xa1280000'
$ setenv ramboot_openwrt 'setenv serverip 192.168.1.66;
tftpboot 0x89000000 1D01A8C0.img; bootm'
$ setenv bootcmd 'run boot_openwrt'
$ saveenv
5. Load OpenWrt into memory:
$ run ramboot_openwrt
6. Transfer the OpenWrt sysupgrade image to the device.
Write the image to flash using sysupgrade:
$ sysupgrade -n /path/to/openwrt-sysupgrade.bin
Signed-off-by: Albin Hellström <albin.hellstrom@gmail.com>
[rename vendor - minor style fixes - update commit message]
Signed-off-by: David Bauer <mail@david-bauer.net>
Older MT7623 ARMv7 SoC as well as new Filogic platforms come with
inside-secure,safexcel-eip97 units. Enable them in DTS and select the
driver kernel module by default on those platforms.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Initially this covers MT7986 only, but it will later be expanded to cover other
Filogic branded platforms by MediaTek
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
It will be supported by the new filogic subtarget
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Use upstream of_get_mtd_device_by_node() which should behave pretty much
the same. Implementation differences:
get_mtd_device_by_node() of_get_mtd_device_by_node()
---- ----
np->dev.of_node mtd_get_of_node(np)
-EPROBE_DEFER -ENODEV
Cc: Bernhard Frauendienst <openwrt@nospam.obeliks.de>
Cc: Bernhard Frauendienst <kernel@nospam.obeliks.de>
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Use new DT clockdriver syntax for RTL838X/RTL839X targets. To make it work
we need to change some nodes:
- define the external oscillator speed (25MHz)
- define SRAM
- add clock controller
- Add second CPU for RTL839X
- map all devices to new clocks
- Remove dummy LXB clock
- add CPU OPP table
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Make use the new clock driver for RTL838X and RTL839x target devices. Of course
we will enable their primary consumer (cpufreq-dt) too. To be careful just set
the default governor to userspace. As we rely on SRAM activate that module too.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
A new clock driver makes more sense if it can be used from consumers
like cpufreq. Before we enable the driver we must tell the config that
the RTL838X and RTL839X targets allow CPU frequency changing.
Even though these targets currently rely on the CPU's internal R4K
timer, MIPS_EXTERNAL_TIMER is selected to allow for CPU frequency change
testing. The Realtek timers, which are clocked by the Lexra bus, still
need to be supported and used in order to provide correct wall times
when reclocking the CPU.
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[add paragraph about MIPS_EXTERNAL_TIMER to commit message]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Add a new self-contained combined clock & platform driver that allows to
access the PLL hardware clocks of RTL83XX devices. Currently it provides
info about CPU, MEM and LXB clocks on RTL838X and RTL839X devices and
additionally allows to change the CPU clocks. Changing the clocks
multiple times on a DGS-1210-20 and a DGS-1210-52 already works well and
is multithreading safe on the RTL839X. Even a cpufreq initiated change
of the CPU clock works fine. Loading the driver will add some meaningful
logging.
[0.000000] rtl83xx-clk: initialized, CPU 500 MHz, MEM 300 MHz (8 Bit DDR3), LXB 200 MHz
[0.279456] rtl83xx-clk soc:clock-controller: rate setting enabled, CPU 325-600 MHz,
MEM 300-300 MHz, LXB 200-200 MHz, OVERCLOCK AT OWN RISK
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
[remove trailing whitespaces, C-style SPDX comments for ASM and headers]
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Fixes following build issue found during build testing with 5.15.63
kernel:
LED Support for Broadcom BCM63138 SoC (LEDS_BCM63138) [N/m/y/?] (NEW)
Signed-off-by: Petr Štetiar <ynezz@true.cz>
Removed following upstreamed patch:
* bcm53xx: 081-next-ARM_dts_BCM53015-add-mr26.patch
All other patches automagically rebased.
Signed-off-by: Petr Štetiar <ynezz@true.cz>
Add missing scaling_available_frequencies sysfs entry for dedicated
cpufreq driver.
This sysfs entry is not standard and each cpufreq driver needs to
provide it and declare it in the cpufreq driver struct attr.
Fixes: 5dbbefcbcc ("ipq806x: introduce dedicated krait cpufreq")
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Specifications:
* AR9342, 16 MiB Flash, 64 MiB RAM, 802.11n 2T2R, 2.4 GHz
* 1x Gigabit Ethernet (AR8035), 802.3af PoE
Installation:
* OEM Web UI is at 192.168.1.2
login as `admin` with password `1234`
* Flash factory-AASI.bin
The string `AASI` needs to be present within the file name of the uploaded
image to be accepted by the OEM Web-based updater, the factory image is
named accordingly to save the user from the hassle of manual renaming.
TFTP Recovery:
* Open the case, connect to TTL UART port (this is the official method
described by Zyxel, the reset button is useless during power-on)
* Extract factory image (.tar.bz2), serve `vmlinux_mi124_f1e.lzma.uImage`
and `mi124_f1e-jffs2` via tftp at 192.168.1.10
* Interrupt uboot countdown, execute commands
`run lk`
`run lf`
to flash the kernel / filesystem accordingly
MAC addresses as verified by OEM firmware:
use address source
LAN *:cc mib0 0x30 ('eth0mac'), art 0x1002 (label)
2g *:cd mib0 0x4b ('wifi0mac')
Signed-off-by: Sebastian Schaper <openwrt@sebastianschaper.net>
Specifications:
* AR9342, 16 MiB Flash, 64 MiB RAM, 802.11n 2T2R, 2.4 GHz
* QCA9882 PCIe card, 802.11ac 2T2R
* 1x Gigabit Ethernet (AR8035), 802.3af PoE
Installation:
* OEM Web UI is at 192.168.1.2
login as `admin` with password `1234`
* Flash factory-AAOX.bin
The string `AAOX` needs to be present within the file name of the uploaded
image to be accepted by the OEM Web-based updater, the factory image is
named accordingly to save the user from the hassle of manual renaming.
TFTP Recovery:
* Open the case, connect to TTL UART port (this is the official method
described by Zyxel, the reset button is useless during power-on)
* Extract factory image (.tar.bz2), serve `vmlinux_mi124_f1e.lzma.uImage`
and `mi124_f1e-jffs2` via tftp at 192.168.1.10
* Interrupt uboot countdown, execute commands
`run lk`
`run lf`
to flash the kernel / filesystem accordingly
MAC addresses as verified by OEM firmware:
use address source
LAN *:1c mib0 0x30 ('eth0mac'), art 0x1002 (label)
2g *:1c mib0 0x4b ('wifi0mac')
5g *:1e mib0 0x66 ('wifi1mac')
Signed-off-by: Sebastian Schaper <openwrt@sebastianschaper.net>
Specifications:
* AR9342, 16 MiB Flash, 64 MiB RAM, 802.11n 2T2R, 2.4 GHz
* AR9382 PCIe card, 802.11n 2T2R, 5 GHz
* 1x Gigabit Ethernet (AR8035), 802.3af PoE
Installation:
* OEM Web UI is at 192.168.1.2
login as `admin` with password `1234`
* Flash factory-AAEO.bin
The string `AAEO` needs to be present within the file name of the uploaded
image to be accepted by the OEM Web-based updater, the factory image is
named accordingly to save the user from the hassle of manual renaming.
TFTP Recovery:
* Open the case, connect to TTL UART port (this is the official method
described by Zyxel, the reset button is useless during power-on)
* Extract factory image (.tar.bz2), serve `vmlinux_mi124_f1e.lzma.uImage`
and `mi124_f1e-jffs2` via tftp at 192.168.1.10
* Interrupt uboot countdown, execute commands
`run lk`
`run lf`
to flash the kernel / filesystem accordingly
MAC addresses as verified by OEM firmware:
use address source
LAN *:fb mib0 0x30 ('eth0mac'), art 0x1002 (label)
2g *:fc mib0 0x4b ('wifi0mac')
5g *:fd mib0 0x66 ('wifi1mac')
Signed-off-by: Sebastian Schaper <openwrt@sebastianschaper.net>
Specifications:
* AR9342, 16 MiB Flash, 64 MiB RAM, 802.11n 2T2R, 2.4 GHz
* 1x Gigabit Ethernet (AR8035), 802.3af PoE
Installation:
* OEM Web UI is at 192.168.1.2
login as `admin` with password `1234`
* Flash factory-AABJ.bin
The string `AABJ` needs to be present within the file name of the uploaded
image to be accepted by the OEM Web-based updater, the factory image is
named accordingly to save the user from the hassle of manual renaming.
TFTP Recovery:
* Open the case, connect to TTL UART port (this is the official method
described by Zyxel, the reset button is useless during power-on)
* Extract factory image (.tar.bz2), serve `vmlinux_mi124_f1e.lzma.uImage`
and `mi124_f1e-jffs2` via tftp at 192.168.1.10
* Interrupt uboot countdown, execute commands
`run lk`
`run lf`
to flash the kernel / filesystem accordingly
MAC addresses as verified by OEM firmware:
use address source
LAN *:cc mib0 0x30 ('eth0mac'), art 0x1002 (label)
2g *:cd mib0 0x4b ('wifi0mac')
Signed-off-by: Sebastian Schaper <openwrt@sebastianschaper.net>
Mux the MT7530 switch's phy0/4 to the SoC's gmac1 on devices where RGMII2
pins are available. This achieves 2 Gbps total bandwidth to the CPU using
the second RGMII.
The ports called "wan" are muxed where possible. On a minority of devices,
this is not possible. Those cases:
mt7621_ampedwireless_ally-r1900k.dts: lan3
mt7621_ubnt_edgerouter-x.dts: eth0
mt7621_gnubee_gb-pc1.dts: ethblue
mt7621_linksys_re6500.dts: lan1
mt7621_netgear_wac104.dts: lan4
mt7621_tplink_eap235-wall-v1.dts: lan0
mt7621_tplink_eap615-wall-v1.dts: lan0
mt7621_ubnt_usw-flex.dts: lan1
The "wan" port is just what the vendor designated on the board/plastic
chasis of the device. On a technical level, there is no difference between
a lan and wan port on MT7621AT, MT7621DAT and MT7621ST SoCs. Prefer
connecting to WAN via the port described above for these devices to benefit
the feature brought with this patch.
mt7621_d-team_newifi-d2.dts cannot benefit this feature, although it looks
like it should, because the rgmii2 pins are wired to unused components.
Tested on a range of devices documented on the GitHub PR.
Link: https://github.com/openwrt/openwrt/pull/10238
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Remove DTS_LEGACY put for claiming pin groups for the ethernet node from
the ethernet node. It's not an old kernel trait. These bindings need to be
there on the newer kernels as well.
Fixes: a3764ee29d ("ramips: add linux 5.15 support for mt7621")
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
These devices do not use rgmii2 as gpio, therefore remove rgmii2 pin group
from state-default. Remove overwriting the ethernet node for these devices.
Move claiming the rgmii2 group from mt7621_zyxel_nwa-ax.dtsi to
mt7621_zyxel_nwa50ax.dts as it's only the latter using rgmii2 pins as gpio.
Remove duplicate ethernet overwrite from mt7621_tplink_archer-x6-v3.dtsi.
Claim rgmii2 group as gpio on mt7621_bolt_arion.dts as it uses an rgmii2
pin, 26, as gpio.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Change switch port labels to ethblack & ethblue.
Change lan1 & lan2 LEDs to ethblack_act & ethblue_act and fix GPIO pins.
Add the external phy with ethyellow label on the GB-PC2 devicetree.
Do not claim rgmii2 as gpio, it's used for ethernet with rgmii2 function.
Enable ICPlus PHY driver for IP1001 which GB-PC2 has got.
Update interface name and change netdev function.
Enable lzma compression to make up for the increased size of the kernel.
Make spi flash bindings on par with mainline Linux to fix read errors.
Tested on GB-PC2 by Petr.
Tested-by: Petr Louda <petr.louda@outlook.cz>
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
