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ramips: mt7620: use DTS to set PHY base address for external PHYs

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Set the PHY base address to 12 for mt7530 and 8 for others,
which is based on the default setting for some devices
from printing the register with the following command
after it is written to by uboot during the boot cycle.

`md 0x10117014 1`

PHY_BASE option only uses 5 bits of the register,
bits 16 to 20, so use 8-bit integer type.

Set the option using the DTS property mediatek,ephy-base
and create the gsw node if missing.

Also, added a kernel message to display the EPHY base address.

Note:
If anything is written to a PHY address that is greater than 1 hex char (greater than 0xf)
then there is adverse effects with Atheros switches.

Signed-off-by: Michael Pratt <mcpratt@pm.me>
(cherry picked from commit 0976b6c426)
This commit is contained in:
Michael Pratt 2021-04-03 14:42:51 -04:00 committed by Petr Štetiar
parent 5d7805c78b
commit 6876465875
24 changed files with 60 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
target/linux/ramips/dts/mt7620a_dlink_dwr-118-a1.dts
View File

@ -186,4 +186,5 @@
&gsw {
mediatek,port4-gmac;
mediatek,ephy-base = /bits/ 8 <8>;
};

2
target/linux/ramips/dts/mt7620a_dlink_dwr-118-a2.dts
View File

@ -174,5 +174,5 @@
&gsw {
mediatek,port4-gmac;
mediatek,ephy-base-address = /bits/ 16 < 2 >;
mediatek,ephy-base = /bits/ 8 <2>;
};

1
target/linux/ramips/dts/mt7620a_dovado_tiny-ac.dts
View File

@ -136,6 +136,7 @@
&gsw {
mediatek,port4-gmac;
mediatek,ephy-base = /bits/ 8 <8>;
};
&pcie {

4
target/linux/ramips/dts/mt7620a_edimax_br-6478ac-v2.dts
View File

@ -177,6 +177,10 @@
};
};
&gsw {
mediatek,ephy-base = /bits/ 8 <12>;
};
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};

4
target/linux/ramips/dts/mt7620a_edimax_ew-7478apc.dts
View File

@ -169,6 +169,10 @@
};
};
&gsw {
mediatek,ephy-base = /bits/ 8 <12>;
};
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};

4
target/linux/ramips/dts/mt7620a_edimax_ew-747x.dtsi
View File

@ -201,6 +201,10 @@
};
};
&gsw {
mediatek,ephy-base = /bits/ 8 <8>;
};
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};

4
target/linux/ramips/dts/mt7620a_engenius_esr600.dts
View File

@ -160,6 +160,10 @@
};
};
&gsw {
mediatek,ephy-base = /bits/ 8 <8>;
};
&state_default {
gpio {
groups = "i2c", "uartf", "nd_sd", "wled";

1
target/linux/ramips/dts/mt7620a_fon_fon2601.dts
View File

@ -137,6 +137,7 @@
&gsw {
mediatek,port4-gmac;
mediatek,ephy-base = /bits/ 8 <8>;
};
&wmac {

1
target/linux/ramips/dts/mt7620a_head-weblink_hdrm200.dts
View File

@ -151,6 +151,7 @@
&gsw {
mediatek,port4-gmac;
mediatek,ephy-base = /bits/ 8 <8>;
};
&wmac {

4
target/linux/ramips/dts/mt7620a_iodata_wn-ac1167gr.dts
View File

@ -184,6 +184,10 @@
};
};
&gsw {
mediatek,ephy-base = /bits/ 8 <12>;
};
&state_default {
gpio {
groups = "i2c", "uartf";

4
target/linux/ramips/dts/mt7620a_iptime_a1004ns.dts
View File

@ -101,3 +101,7 @@
};
};
};
&gsw {
mediatek,ephy-base = /bits/ 8 <12>;
};

4
target/linux/ramips/dts/mt7620a_lava_lr-25g001.dts
View File

@ -150,6 +150,10 @@
};
};
&gsw {
mediatek,ephy-base = /bits/ 8 <8>;
};
&pcie {
status = "okay";
};

4
target/linux/ramips/dts/mt7620a_lb-link_bl-w1200.dts
View File

@ -135,6 +135,10 @@
};
};
&gsw {
mediatek,ephy-base = /bits/ 8 <12>;
};
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};

1
target/linux/ramips/dts/mt7620a_lenovo_newifi-y1s.dts
View File

@ -112,4 +112,5 @@
&gsw {
mediatek,port4-gmac;
mediatek,ephy-base = /bits/ 8 <8>;
};

4
target/linux/ramips/dts/mt7620a_linksys_e1700.dts
View File

@ -144,6 +144,10 @@
};
};
&gsw {
mediatek,ephy-base = /bits/ 8 <12>;
};
&wmac {
ralink,mtd-eeprom = <&factory 0x0>;
};

4
target/linux/ramips/dts/mt7620a_netis_wf2770.dts
View File

@ -142,6 +142,10 @@
};
};
&gsw {
mediatek,ephy-base = /bits/ 8 <12>;
};
&pcie {
status = "okay";
};

1
target/linux/ramips/dts/mt7620a_ralink_mt7620a-evb.dts
View File

@ -106,6 +106,7 @@
&gsw {
mediatek,port4-gmac;
mediatek,ephy-base = /bits/ 8 <8>;
};
&sdhci {

4
target/linux/ramips/dts/mt7620a_ralink_mt7620a-mt7530-evb.dts
View File

@ -99,6 +99,10 @@
};
};
&gsw {
mediatek,ephy-base = /bits/ 8 <12>;
};
&pcie {
status = "okay";
};

1
target/linux/ramips/dts/mt7620a_ralink_mt7620a-v22sg-evb.dts
View File

@ -100,6 +100,7 @@
&gsw {
mediatek,port4-gmac;
mediatek,ephy-base = /bits/ 8 <8>;
};
&pcie {

1
target/linux/ramips/dts/mt7620a_sercomm_na930.dts
View File

@ -167,6 +167,7 @@
&gsw {
mediatek,port4-gmac;
mediatek,ephy-base = /bits/ 8 <8>;
};
&ehci {

1
target/linux/ramips/dts/mt7620a_tplink_re210-v1.dts
View File

@ -62,6 +62,7 @@
&gsw {
mediatek,port4-gmac;
mediatek,ephy-base = /bits/ 8 <8>;
};
&ethernet {

1
target/linux/ramips/dts/mt7620a_wavlink_wl-wn579x3.dts
View File

@ -196,6 +196,7 @@
&gsw {
mediatek,port4-gmac;
mediatek,ephy-base = /bits/ 8 <8>;
};
&wmac {

1
target/linux/ramips/dts/mt7620a_zyxel_keenetic-viva.dts
View File

@ -158,6 +158,7 @@
&gsw {
mediatek,port4-gmac;
mediatek,ephy-base = /bits/ 8 <8>;
};
&wmac {

10
target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c
View File

@ -98,9 +98,6 @@ static void mt7620_hw_init(struct mt7620_gsw *gsw, int mdio_mode)
mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_MIB_CNT_EN) | (1 << 1), GSW_REG_MIB_CNT_EN);
if (mdio_mode) {
if (!gsw->ephy_base)
gsw->ephy_base = 12;
/* set MT7530 central align */
val = mt7530_mdio_r32(gsw, 0x7830);
val &= ~BIT(0);
@ -115,11 +112,12 @@ static void mt7620_hw_init(struct mt7620_gsw *gsw, int mdio_mode)
}
if (gsw->ephy_base) {
/* set phy base addr to ephy_base */
mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
(gsw->ephy_base << 16),
GSW_REG_GPC1);
fe_reset(BIT(24)); /* Resets the Ethernet PHY block. */
pr_info("gsw: ephy base address: %d\n", gsw->ephy_base);
}
/* global page 4 */
@ -246,7 +244,7 @@ static int mt7620_gsw_probe(struct platform_device *pdev)
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
struct mt7620_gsw *gsw;
struct device_node *np = pdev->dev.of_node;
u16 val;
u8 val;
gsw = devm_kzalloc(&pdev->dev, sizeof(struct mt7620_gsw), GFP_KERNEL);
if (!gsw)
@ -260,7 +258,7 @@ static int mt7620_gsw_probe(struct platform_device *pdev)
gsw->port4_ephy = !of_property_read_bool(np, "mediatek,port4-gmac");
if (of_property_read_u16(np, "mediatek,ephy-base-address", &val) == 0)
if (of_property_read_u8(np, "mediatek,ephy-base", &val) == 0)
gsw->ephy_base = val;
else
gsw->ephy_base = 0;