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6876465875
Set the PHY base address to 12 for mt7530 and 8 for others,
which is based on the default setting for some devices
from printing the register with the following command
after it is written to by uboot during the boot cycle.
`md 0x10117014 1`
PHY_BASE option only uses 5 bits of the register,
bits 16 to 20, so use 8-bit integer type.
Set the option using the DTS property mediatek,ephy-base
and create the gsw node if missing.
Also, added a kernel message to display the EPHY base address.
Note:
If anything is written to a PHY address that is greater than 1 hex char (greater than 0xf)
then there is adverse effects with Atheros switches.
Signed-off-by: Michael Pratt <mcpratt@pm.me>
(cherry picked from commit 0976b6c426)
176 lines
2.7 KiB
Plaintext
176 lines
2.7 KiB
Plaintext
#include "mt7620a.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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compatible = "lava,lr-25g001", "ralink,mt7620a-soc";
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model = "LAVA LR-25G001";
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aliases {
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led-boot = &led_status;
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led-failsafe = &led_status;
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led-running = &led_status;
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led-upgrade = &led_status;
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};
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keys {
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compatible = "gpio-keys";
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wps {
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label = "wps";
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gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_WPS_BUTTON>;
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};
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reset {
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label = "reset";
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gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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leds {
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compatible = "gpio-leds";
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led_status: status {
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label = "green:status";
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gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
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};
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wifi2g {
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label = "green:wifi2g";
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gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
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};
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wifi5g {
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label = "green:wifi5g";
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gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
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};
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};
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gpio_export {
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compatible = "gpio-export";
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#size-cells = <0>;
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usbpower {
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gpio-export,name = "usbpower";
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gpio-export,output = <1>;
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gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
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};
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "jboot";
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reg = <0x0 0x10000>;
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read-only;
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};
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partition@10000 {
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compatible = "amit,jimage";
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label = "firmware";
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reg = <0x10000 0xfe0000>;
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};
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config: partition@ff0000 {
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label = "config";
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reg = <0xff0000 0x10000>;
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read-only;
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};
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};
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};
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};
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&ehci {
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status = "okay";
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};
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&ohci {
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status = "okay";
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};
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ðernet {
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
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port@5 {
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status = "okay";
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phy-mode = "rgmii";
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mediatek,fixed-link = <1000 1 1 1>;
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};
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mdio-bus {
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status = "okay";
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mediatek,mdio-mode = <1>;
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phy0: ethernet-phy@0 {
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reg = <0>;
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phy-mode = "rgmii";
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qca,ar8327-initvals = <
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0x04 0x87300000 /* PORT0 PAD MODE CTRL */
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0x0c 0x00000000 /* PORT6 PAD MODE CTRL */
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0x7c 0x0000007e /* PORT0_STATUS */
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0x94 0x00000000 /* PORT6_STATUS */
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>;
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};
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phy1: ethernet-phy@1 {
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reg = <1>;
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phy-mode = "rgmii";
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};
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phy2: ethernet-phy@2 {
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reg = <2>;
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phy-mode = "rgmii";
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};
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phy3: ethernet-phy@3 {
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reg = <3>;
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phy-mode = "rgmii";
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};
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phy4: ethernet-phy@4 {
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reg = <4>;
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phy-mode = "rgmii";
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};
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};
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};
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&gsw {
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mediatek,ephy-base = /bits/ 8 <8>;
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};
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&pcie {
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status = "okay";
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};
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&pcie0 {
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mt76x0e@0,0 {
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reg = <0x0000 0 0 0 0>;
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mtd-mac-address = <&config 0xe07e>;
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mtd-mac-address-increment = <(2)>;
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mediatek,mtd-eeprom = <&config 0xe08a>;
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};
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};
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&state_default {
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gpio {
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groups = "uartf", "i2c";
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function = "gpio";
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};
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};
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