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uboot-sunxi: bump to 2023.04

Browse Source 
Compile-tested: all boards
Runtime-tested:
 - Cortex-A8: pcDuino
 - Cortex-A7: Bananapro, Bananapi M3
 - Cortex-A53:Pine64+

Notes:
 - binman tries to add firmware for the SCP (system control processor), which
   we don't build, and is optional for the boot process on 64-bit. Disable this
   via setting the SCP envvar to /dev/null. For further info, see [1] .

[1] https://github.com/u-boot/u-boot/blob/master/board/sunxi/README.sunxi64

Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
This commit is contained in:
Zoltan HERPAI 2023-06-07 12:13:11 +02:00
parent 8b1cc1582a
commit 53c2f174ad
17 changed files with 39 additions and 1150 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
package/boot/uboot-sunxi/Makefile
View File

@ -9,9 +9,9 @@
include $(TOPDIR)/rules.mk include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk include $(INCLUDE_DIR)/kernel.mk
PKG_VERSION:=2020.07 PKG_VERSION:=2023.04
PKG_HASH:=c1f5bf9ee6bb6e648edbf19ce2ca9452f614b08a9f886f1a566aa42e8cf05f6a PKG_HASH:=e31cac91545ff41b71cec5d8c22afd695645cd6e2a442ccdacacd60534069341
PKG_MAINTAINER:=Zoltan HERPAI <wigyori@uid0.hu> PKG_MAINTAINER:=Zoltan HERPAI <wigyori@uid0.hu>
@ -392,7 +392,7 @@ UBOOT_TARGETS := \
UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes
UBOOT_MAKE_FLAGS += \ UBOOT_MAKE_FLAGS += \
BL31=$(STAGING_DIR_IMAGE)/bl31_sunxi-$(ATF).bin BL31=$(STAGING_DIR_IMAGE)/bl31_sunxi-$(ATF).bin SCP=/dev/null
define Build/InstallDev define Build/InstallDev
$(INSTALL_DIR) $(STAGING_DIR_IMAGE) $(INSTALL_DIR) $(STAGING_DIR_IMAGE)

375
package/boot/uboot-sunxi/patches/003-add-theobroma-a31-pangolin.patch
View File

@ -1,375 +0,0 @@
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -475,6 +475,7 @@ dtb-$(CONFIG_MACH_SUN6I) += \
sun6i-a31-m9.dtb \
sun6i-a31-mele-a1000g-quad.dtb \
sun6i-a31-mixtile-loftq.dtb \
+ sun6i-a31-pangolin.dtb \
sun6i-a31s-colorfly-e708-q1.dtb \
sun6i-a31s-cs908.dtb \
sun6i-a31s-inet-q972.dtb \
--- a/arch/arm/dts/sun6i-a31.dtsi
+++ b/arch/arm/dts/sun6i-a31.dtsi
@@ -641,6 +641,11 @@
function = "lcd0";
};
+ i2c3_pins_a: i2c3@0 {
+ allwinner,pins = "PB5", "PB6";
+ allwinner,function = "i2c3";
+ };
+
mmc0_pins_a: mmc0@0 {
pins = "PF0", "PF1", "PF2",
"PF3", "PF4", "PF5";
--- /dev/null
+++ b/arch/arm/dts/sun6i-a31-pangolin.dts
@@ -0,0 +1,292 @@
+/*
+ * Copyright 2015, Theobroma Systems Design und Consulting GmbH
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun6i-a31.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Theobroma Systems A31 Pangolin";
+ compatible = "tsd,a31-pangolin", "allwinner,sun6i-a31";
+
+ aliases {
+ serial0 = &uart0;
+ serial2 = &uart2;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ spi2 = &spi2;
+ spi3 = &spi3;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_rgmii_a>;
+ phy = <&phy1>;
+ phy-mode = "rgmii";
+ snps,reset-gpio = <&pio 0 7 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 30000>;
+ status = "okay";
+
+ phy1: ethernet-phy@4 {
+ reg = <4>;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins_a>;
+ status = "okay";
+
+ rtc_twi: rtc@6f {
+ compatible = "isil,isl1208";
+ reg = <0x6f>;
+ };
+ fan: fan@18 {
+ compatible = "ti,amc6821";
+ reg = <0x18>;
+ cooling-min-state = <0>;
+ cooling-max-state = <9>;
+ #cooling-cells = <2>;
+ };
+};
+
+&spi0 {
+ status = "okay";
+
+ flash: flash@0 {
+ compatible = "spansion,m25p40";
+ spi-max-frequency = <16000000>;
+ spi-cpol;
+ spi-cpha;
+ };
+};
+
+&spi1 {
+ status = "okay";
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_pangolin>;
+ vmmc-supply = <&reg_vcc3v0>;
+ bus-width = <4>;
+ cd-gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; /* PC19 */
+ status = "okay";
+};
+
+&mmc0_pins_a {
+ /* external pull-ups missing for some pins */
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins_a>;
+ vmmc-supply = <&reg_vcc3v0>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&pio {
+ mmc0_cd_pin_pangolin: mmc0_cd_pin@0 {
+ allwinner,pins = "PC19";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ leds_pins_pangolin: led_pins@0 {
+ allwinner,pins = "PH7", "PC16";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_20_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc2_pins_a: mmc2@0 {
+ allwinner,pins = "PC6","PC7","PC8","PC9","PC10","PC11",
+ "PC12","PC13","PC14","PC15";
+ allwinner,function = "mmc2";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+&p2wi {
+ status = "okay";
+
+ axp221: pmic@68 {
+ compatible = "x-powers,axp221";
+ reg = <0x68>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ dcdc1-supply = <&vcc_3v0>;
+ dcdc5-supply = <&vcc_dram>;
+
+ regulators {
+ x-powers,dcdc-freq = <3000>;
+
+ vcc_3v0: dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-3v0";
+ };
+
+ vdd_cpu: dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd-cpu";
+ };
+
+ vdd_gpu: dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd-gpu";
+ };
+
+ vdd_sys_dll: dcdc4 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-sys-dll";
+ };
+
+ vcc_dram: dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+ };
+
+ vcc_wifi: aldo1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_wifi";
+ };
+
+ avcc: aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+ };
+ };
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usb1_vbus_pin_a {
+ allwinner,pins = "PD23";
+};
+
+&reg_usb1_vbus {
+ gpio = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD 23 */
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+ usb1_vbus-supply = <&reg_usb1_vbus>;
+};
--- /dev/null
+++ b/configs/pangolin_defconfig
@@ -0,0 +1,36 @@
+CONFIG_SUNXI_PANGOLIN=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC,RGMII"
+CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-pangolin"
+CONFIG_VIDEO_VGA_VIA_LCD=y
+CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25"
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN6I=y
+CONFIG_DRAM_CHANNELS=1
+CONFIG_DRAM_CLK=360
+CONFIG_DRAM_ZQ=70
+CONFIG_AXP_DCDC1_VOLT=3300
+CONFIG_AXP_ALDO1_VOLT=0
+CONFIG_AXP_ALDO2_VOLT=1800
+CONFIG_AXP_ALDO3_VOLT=3000
+CONFIG_AXP_DLDO4_VOLT=3300
+CONFIG_AXP_ELDO1_VOLT=1200
+CONFIG_AXP_ELDO2_VOLT=2500
+CONFIG_AXP_ELDO3_VOLT=3300
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_CONS_INDEX=3
+# Vbus gpio for usb1
+CONFIG_USB1_VBUS_PIN=""
+# No Vbus gpio for usb2
+CONFIG_USB2_VBUS_PIN=""
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_DM_ETH=y
+CONFIG_CMD_IMLS=n
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SUNXI_SPI=y
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -896,6 +896,14 @@ config VIDEO_LCD_PANEL_I2C_SCL
Set the SCL pin for the LCD i2c interface. This takes a string in the
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
+choice
+ prompt "Sunxi Board Variant"
+ optional
+
+config SUNXI_PANGOLIN
+ bool "Theobroma A31 uQ7 Board"
+
+endchoice
# Note only one of these may be selected at a time! But hidden choices are
# not supported by Kconfig

2
package/boot/uboot-sunxi/patches/062-A20-improve-gmac-upload.patch
View File

@ -2,7 +2,7 @@
--- a/configs/A20-OLinuXino-Lime2_defconfig --- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig +++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -23,6 +23,7 @@ CONFIG_ETH_DESIGNWARE=y @@ -26,6 +26,7 @@ CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y CONFIG_RGMII=y
CONFIG_MII=y CONFIG_MII=y
CONFIG_SUN7I_GMAC=y CONFIG_SUN7I_GMAC=y

44
package/boot/uboot-sunxi/patches/063-fix-lime2-revK-add-micrel-PHY.patch
View File

@ -1,44 +0,0 @@
--- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
+++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
@@ -8,6 +8,8 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB0_VBUS_PIN="PC17"
CONFIG_USB0_VBUS_DET="PH5"
CONFIG_I2C1_ENABLE=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_SATAPWR="PC3"
CONFIG_SPL_SPI_SUNXI=y
CONFIG_AHCI=y
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -7,6 +7,8 @@ CONFIG_MMC0_CD_PIN="PH1"
CONFIG_USB0_VBUS_PIN="PC17"
CONFIG_USB0_VBUS_DET="PH5"
CONFIG_I2C1_ENABLE=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
--- a/drivers/net/phy/micrel_ksz90x1.c
+++ b/drivers/net/phy/micrel_ksz90x1.c
@@ -14,6 +14,8 @@
#include <errno.h>
#include <micrel.h>
#include <phy.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
/*
* KSZ9021 - KSZ9031 common
@@ -344,6 +346,10 @@ static int ksz9031_phy_extwrite(struct p
static int ksz9031_config(struct phy_device *phydev)
{
int ret;
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_DELAY(4));
ret = ksz9031_of_config(phydev);
if (ret)

2
package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch
View File

@ -14,7 +14,7 @@ More specifically, the following settings are now used:
--- a/arch/arm/mach-sunxi/clock_sun6i.c --- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -114,11 +114,12 @@ void clock_set_pll1(unsigned int clk) @@ -131,11 +131,12 @@ void clock_set_pll1(unsigned int clk)
struct sunxi_ccm_reg * const ccm = struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE; (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
const int p = 0; const int p = 0;

6
package/boot/uboot-sunxi/patches/093-sun6i-fix-PLL-LDO-voltselect.patch
View File

@ -18,7 +18,7 @@ required setting for the PLL LDO is 1.37v as per the A31 manual.
--- a/arch/arm/mach-sunxi/clock_sun6i.c --- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c +++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -27,13 +27,26 @@ void clock_init_safe(void) @@ -28,13 +28,26 @@ void clock_init_safe(void)
struct sunxi_prcm_reg * const prcm = struct sunxi_prcm_reg * const prcm =
(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
@ -47,8 +47,8 @@ required setting for the PLL LDO is 1.37v as per the A31 manual.
#endif #endif
#if defined(CONFIG_MACH_SUN8I_R40) || defined(CONFIG_MACH_SUN50I) #if defined(CONFIG_MACH_SUN8I_R40) || defined(CONFIG_MACH_SUN50I)
--- a/arch/arm/include/asm/arch-sunxi/prcm.h --- a/arch/arm/include/asm/arch-sunxi/prcm_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/prcm.h +++ b/arch/arm/include/asm/arch-sunxi/prcm_sun6i.h
@@ -110,13 +110,13 @@ @@ -110,13 +110,13 @@
#define PRCM_PLL_CTRL_LDO_OUT_MASK \ #define PRCM_PLL_CTRL_LDO_OUT_MASK \
__PRCM_PLL_CTRL_LDO_OUT(0x7) __PRCM_PLL_CTRL_LDO_OUT(0x7)

16
package/boot/uboot-sunxi/patches/100-sun6i-alternate-on-UART2.patch
View File

@ -1,16 +0,0 @@
From d7311b6e7cdd1fc0e92665188e650934718cb2b1 Mon Sep 17 00:00:00 2001
From: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Date: Tue, 16 Jun 2015 10:52:01 +0200
Subject: sun6i: define alternate-function for UART2 on GPG
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -190,6 +190,7 @@ enum sunxi_gpio_number {
#define SUN6I_GPG_SDC1 2
#define SUN8I_GPG_SDC1 2
#define SUN6I_GPG_TWI3 2
+#define SUN6I_GPG_UART2 2
#define SUN5I_GPG_UART1 4
#define SUN6I_GPH_PWM 2

30
package/boot/uboot-sunxi/patches/101-sun6i-support-console-on-UART2.patch
View File

@ -1,30 +0,0 @@
From c058dfb69136d62f88ae8b121104bdb7ce2df03f Mon Sep 17 00:00:00 2001
From: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Date: Tue, 16 Jun 2015 10:53:11 +0200
Subject: ARM: sun6i: Support console on UART2 (GPG6/GPG7)
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -132,6 +132,10 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN6I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPG(6), SUN6I_GPG_UART2);
+ sunxi_gpio_set_cfgpin(SUNXI_GPG(7), SUN6I_GPG_UART2);
+ sunxi_gpio_set_pull(SUNXI_GPG(7), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -244,6 +244,8 @@ extern int soft_i2c_gpio_scl;
#endif
#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28400:115200"
+#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN6I)
+#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28800:115200"
#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28800:115200"
#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)

23
package/boot/uboot-sunxi/patches/102-sunxi-make_CONS_INDEX-configurable.patch
View File

@ -1,23 +0,0 @@
From 78d5fab8e345b1273ec8c22d06f1a1d27670b518 Mon Sep 17 00:00:00 2001
From: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Date: Tue, 16 Jun 2015 10:59:38 +0200
Subject: ARM: sunxi: Make CONS_INDEX configurable
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -559,6 +559,14 @@ config SYS_BOARD
config SYS_SOC
default "sunxi"
+config CONS_INDEX
+ int "UART used for console"
+ range 1 5
+ default 1
+ ---help---
+ Defines the UART port used for serial output. It starts at 1 so UART0 is 1,
+ UART1 is 2 and so on.
+
config UART0_PORT_F
bool "UART0 on MicroSD breakout board"
default n

2
package/boot/uboot-sunxi/patches/200-mkimage-check-environment-for-dtc-binary-location.patch
View File

@ -17,7 +17,7 @@ Cc: Simon Glass <sjg@chromium.org>
--- a/tools/fit_image.c --- a/tools/fit_image.c
+++ b/tools/fit_image.c +++ b/tools/fit_image.c
@@ -751,9 +751,14 @@ static int fit_handle_file(struct image_ @@ -754,9 +754,14 @@ static int fit_handle_file(struct image_
} }
*cmd = '\0'; *cmd = '\0';
} else if (params->datafile) { } else if (params->datafile) {

37
package/boot/uboot-sunxi/patches/210-sunxi-deactivate-binman.patch
View File

@ -1,37 +0,0 @@
From def280c4792262a368c8861312dc6b376181021f Mon Sep 17 00:00:00 2001
From: Hauke Mehrtens <hauke@hauke-m.de>
Date: Mon, 1 Jan 2018 23:10:56 +0100
Subject: sunxi: deactivate binman
Use the old way to generate the images instead of binman.
binman needs python with swig to avoid this host tool dependency use the
old way of generating images.
---
Makefile | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
--- a/Makefile
+++ b/Makefile
@@ -1607,8 +1607,10 @@ endif
ifneq ($(CONFIG_ARCH_SUNXI),)
ifeq ($(CONFIG_ARM64),)
-u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img u-boot.dtb FORCE
- $(call if_changed,binman)
+OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
+ --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
+u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img FORCE
+ $(call if_changed,pad_cat)
else
u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.itb FORCE
$(call if_changed,cat)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -995,7 +995,6 @@ config ARCH_SOCFPGA
config ARCH_SUNXI
bool "Support sunxi (Allwinner) SoCs"
- select BINMAN
select CMD_GPIO
select CMD_MMC if MMC
select CMD_USB if DISTRO_DEFAULTS

19
package/boot/uboot-sunxi/patches/230-disable-axp209-on-a13-olinuxino.diff
View File

@ -1,19 +0,0 @@
--- a/configs/A13-OLinuXino_defconfig
+++ b/configs/A13-OLinuXino_defconfig
@@ -7,7 +7,6 @@ CONFIG_DRAM_EMR1=0
CONFIG_MMC0_CD_PIN="PG0"
CONFIG_USB0_VBUS_DET="PG1"
CONFIG_USB1_VBUS_PIN="PG11"
-CONFIG_AXP_GPIO=y
# CONFIG_VIDEO_HDMI is not set
CONFIG_VIDEO_VGA_VIA_LCD=y
CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y
@@ -20,7 +19,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino"
CONFIG_DFU_RAM=y
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_AXP_ALDO3_VOLT=3300
+CONFIG_SUNXI_NO_PMIC=y
CONFIG_CONS_INDEX=2
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y

148
package/boot/uboot-sunxi/patches/250-sun8i-h3-add-support-for-zeropi.patch
View File

@ -1,148 +0,0 @@
From 2527b24f39d8f27ba2fd922ca27a1f14119cfa1b Mon Sep 17 00:00:00 2001
From: Yu-Tung Chang <mtwget@gmail.com>
Date: Sat, 19 Jun 2021 16:16:45 +0800
Subject: [PATCH] sunxi: h3: Add initial ZeroPi support
ZeroPi is a new board of high performance with low cost
designed by FriendlyElec., using the Allwinner H3 SOC.
ZeroPi features
- Allwinner H3, Quad-core Cortex-A7@1.2GHz
- 256MB/512MB DDR3 RAM
- microsd slot
- 10/100/1000Mbps Ethernet
- Debug Serial Port
- DC 5V/2A power-supply
Signed-off-by: Yu-Tung Chang <mtwget@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -560,7 +560,8 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
sun8i-h3-orangepi-plus.dtb \
sun8i-h3-orangepi-plus2e.dtb \
sun8i-h3-orangepi-zero-plus2.dtb \
- sun8i-h3-rervision-dvk.dtb
+ sun8i-h3-rervision-dvk.dtb \
+ sun8i-h3-zeropi.dtb
dtb-$(CONFIG_MACH_SUN8I_R40) += \
sun8i-r40-bananapi-m2-ultra.dtb \
sun8i-v40-bananapi-m2-berry.dtb
--- /dev/null
+++ b/arch/arm/dts/sun8i-h3-zeropi.dts
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2020 Yu-Tung Chang <mtwget@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sun8i-h3-nanopi.dtsi"
+
+/ {
+ model = "FriendlyARM ZeroPi";
+ compatible = "friendlyarm,zeropi", "allwinner,sun8i-h3";
+
+ aliases {
+ ethernet0 = &emac;
+ };
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
+ };
+};
+
+&external_mdio {
+ ext_rgmii_phy: ethernet-phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ };
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <&reg_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii-id";
+
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
+&usb_otg {
+ status = "okay";
+ dr_mode = "host";
+};
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -508,3 +508,9 @@ YONES TOPTECH BS1078 V2 BOARD
M: Peter Korsgaard <peter@korsgaard.com>
S: Maintained
F: configs/Yones_Toptech_BS1078_V2_defconfig
+
+ZEROPI BOARD
+M: Yu-Tung Chang <mtwget@gmail.com>
+S: Maintained
+F: configs/zeropi_defconfig
+F: arch/arm/dts/sun8i-h3-zeropi.dts
--- /dev/null
+++ b/configs/zeropi_defconfig
@@ -0,0 +1,13 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-zeropi"
+CONFIG_SPL=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=408
+CONFIG_MACPWR="PD6"
+# CONFIG_VIDEO_DE2 is not set
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_CONSOLE_MUX=y
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y

159
package/boot/uboot-sunxi/patches/252-sunxi-h3-add-support-for-nanopi-r1.patch
View File

@ -12,165 +12,6 @@ Signed-off-by: Jayantajit Gogoi <jayanta.gogoi525@gmail.com>
create mode 100644 arch/arm/dts/sun8i-h3-nanopi-r1.dts create mode 100644 arch/arm/dts/sun8i-h3-nanopi-r1.dts
create mode 100644 configs/nanopi_r1_defconfig create mode 100644 configs/nanopi_r1_defconfig
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -551,6 +551,7 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
sun8i-h3-nanopi-m1-plus.dtb \
sun8i-h3-nanopi-neo.dtb \
sun8i-h3-nanopi-neo-air.dtb \
+ sun8i-h3-nanopi-r1.dtb \
sun8i-h3-orangepi-2.dtb \
sun8i-h3-orangepi-lite.dtb \
sun8i-h3-orangepi-one.dtb \
--- /dev/null
+++ b/arch/arm/dts/sun8i-h3-nanopi-r1.dts
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Igor Pecovnik <igor@armbian.com>
+ * Copyright (C) 2020 Jayantajit Gogoi <jayanta.gogoi525@gmail.com>
+ */
+
+/* NanoPi R1 is based on the NanoPi-H3 design from FriendlyARM */
+#include "sun8i-h3-nanopi.dtsi"
+
+/ {
+ model = "FriendlyARM NanoPi R1";
+ compatible = "friendlyarm,nanopi-r1", "allwinner,sun8i-h3";
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ vdd_cpux: gpio-regulator {
+ compatible = "regulator-gpio";
+ pinctrl-names = "default";
+ regulator-name = "vdd-cpux";
+ regulator-type = "voltage";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-ramp-delay = <50>;
+ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0x1>;
+ states = <1100000 0x0
+ 1300000 0x1>;
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>;
+ };
+
+ leds {
+ /delete-node/ pwr;
+ status {
+ label = "nanopi:red:status";
+ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ wan {
+ label = "nanopi:green:wan";
+ gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>;
+ };
+
+ lan {
+ label = "nanopi:green:lan";
+ gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ r_gpio_keys {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sw_r_npi>;
+
+ /delete-node/ k1;
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpux>;
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <&reg_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii";
+ status = "okay";
+};
+
+&external_mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ };
+};
+
+&mmc1 {
+ vmmc-supply = <&reg_vcc3v3>;
+ vqmmc-supply = <&reg_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ sdio_wifi: sdio_wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&pio>;
+ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "host-wake";
+ };
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ vqmmc-supply = <&reg_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&r_pio {
+ sw_r_npi: key_pins {
+ pins = "PL3";
+ function = "gpio_in";
+ };
+};
--- /dev/null --- /dev/null
+++ b/configs/nanopi_r1_defconfig +++ b/configs/nanopi_r1_defconfig
@@ -0,0 +1,21 @@ @@ -0,0 +1,21 @@

261
package/boot/uboot-sunxi/patches/253-sunxi-h5-add-support-for-nanopi-r1s-h5.patch
View File

@ -1,261 +0,0 @@
From e7510d24cab4741f72489b9d67c2d42b18fe5374 Mon Sep 17 00:00:00 2001
From: Chukun Pan <amadeus@jmu.edu.cn>
Date: Sun, 10 Oct 2021 21:36:57 +0800
Subject: [PATCH] sunxi: Add support for FriendlyARM NanoPi R1S H5
This adds support for the NanoPi R1S H5 board.
Allwinner H5 SoC
512MB DDR3 RAM
10/100/1000M Ethernet x 2
RTL8189ETV WiFi 802.11b/g/n
USB 2.0 host port (A)
MicroSD Slot
Reset button
Serial Debug Port
WAN - LAN - SYS LED
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts | 195 +++++++++++++++++++++++
board/sunxi/MAINTAINERS | 5 +
configs/nanopi_r1s_h5_defconfig | 14 ++
4 files changed, 215 insertions(+)
create mode 100644 arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts
create mode 100644 configs/nanopi_r1s_h5_defconfig
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -575,6 +575,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \
sun50i-h5-libretech-all-h5-cc.dtb \
sun50i-h5-nanopi-neo2.dtb \
sun50i-h5-nanopi-neo-plus2.dtb \
+ sun50i-h5-nanopi-r1s-h5.dtb \
sun50i-h5-orangepi-zero-plus.dtb \
sun50i-h5-orangepi-pc2.dtb \
sun50i-h5-orangepi-prime.dtb \
--- /dev/null
+++ b/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 Chukun Pan <amadeus@jmu.edu.cn>
+ *
+ * Based on sun50i-h5-nanopi-neo-plus2.dts, which is:
+ * Copyright (C) 2017 Antony Antony <antony@phenome.org>
+ * Copyright (C) 2016 ARM Ltd.
+ */
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "FriendlyARM NanoPi R1S H5";
+ compatible = "friendlyarm,nanopi-r1s-h5", "allwinner,sun50i-h5";
+
+ aliases {
+ ethernet0 = &emac;
+ ethernet1 = &rtl8189etv;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ sys {
+ label = "nanopi:red:sys";
+ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ lan {
+ label = "nanopi:green:lan";
+ gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>;
+ };
+
+ wan {
+ label = "nanopi:green:wan";
+ gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ r-gpio-keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_usb0_vbus: usb0-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
+ status = "okay";
+ };
+
+ vdd_cpux: gpio-regulator {
+ compatible = "regulator-gpio";
+ regulator-name = "vdd-cpux";
+ regulator-type = "voltage";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-ramp-delay = <50>; /* 4ms */
+ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0x1>;
+ states = <1100000 0x0>, <1300000 0x1>;
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
+ post-power-on-delay-ms = <200>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpux>;
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <&reg_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
+
+&external_mdio {
+ ext_rgmii_phy: ethernet-phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@51 {
+ compatible = "microchip,24c02";
+ reg = <0x51>;
+ pagesize = <16>;
+ };
+};
+
+&mmc0 {
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <&reg_vcc3v3>;
+ vqmmc-supply = <&reg_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ rtl8189etv: sdio_wifi@1 {
+ reg = <1>;
+ };
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pa_pins>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ /* USB Type-A port's VBUS is always on */
+ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+ usb0_vbus-supply = <&reg_usb0_vbus>;
+ status = "okay";
+};
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -358,6 +358,11 @@ M: Jelle van der Waa <jelle@vdwaa.nl>
S: Maintained
F: configs/nanopi_neo_air_defconfig
+NANOPI-R1S-H5 BOARD
+M: Chukun Pan <amadeus@jmu.edu.cn>
+S: Maintained
+F: configs/nanopi_r1s_h5_defconfig
+
NANOPI-A64 BOARD
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
--- /dev/null
+++ b/configs/nanopi_r1s_h5_defconfig
@@ -0,0 +1,14 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SPL=y
+CONFIG_MACH_SUN50I_H5=y
+CONFIG_DRAM_CLK=672
+CONFIG_DRAM_ZQ=3881977
+# CONFIG_DRAM_ODT_EN is not set
+CONFIG_MACPWR="PD6"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-r1s-h5"
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y

29
package/boot/uboot-sunxi/patches/270-arm-sunxi-increase-SYS_MALLOC_F_LEN.patch
View File

@ -1,29 +0,0 @@
From 20abdd7feefbb4fccef5c653e045911670237e8b Mon Sep 17 00:00:00 2001
From: Stijn Tintel <stijn@linux-ipv6.be>
Date: Thu, 22 Dec 2022 00:35:07 +0200
Subject: [PATCH] arm: sunxi: increase SYS_MALLOC_F_LEN
Version 2020.10 throws the following output after loading bl31:
alloc space exhausted
This has been fixed in v2022.07, but the change is too intrusive to
backport. Instead, just modify the default for ARCH_SUNXI for now.
See e05689242238 ("Kconfig: Change SYS_MALLOC_F_LEN default to 0x2000").
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
---
Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/Kconfig
+++ b/Kconfig
@@ -146,7 +146,7 @@ config SYS_MALLOC_F_LEN
default 0x2000 if (ARCH_IMX8 || ARCH_IMX8M || ARCH_MX7 || \
ARCH_MX7ULP || ARCH_MX6 || ARCH_MX5 || \
ARCH_LS1012A || ARCH_LS1021A || ARCH_LS1043A || \
- ARCH_LS1046A || ARCH_QEMU)
+ ARCH_LS1046A || ARCH_QEMU || ARCH_SUNXI)
default 0x400
help
Before relocation, memory is very limited on many platforms. Still,

30
package/boot/uboot-sunxi/patches/300-force-pylibfdt-build.patch Normal file
View File

@ -0,0 +1,30 @@
--- a/Makefile
+++ b/Makefile
@@ -2000,26 +2000,7 @@ endif
# Check dtc and pylibfdt, if DTC is provided, else build them
PHONY += scripts_dtc
scripts_dtc: scripts_basic
- $(Q)if test "$(DTC)" = "$(DTC_INTREE)"; then \
- $(MAKE) $(build)=scripts/dtc; \
- else \
- if ! $(DTC) -v >/dev/null; then \
- echo '*** Failed to check dtc version: $(DTC)'; \
- false; \
- else \
- if test "$(call dtc-version)" -lt $(DTC_MIN_VERSION); then \
- echo '*** Your dtc is too old, please upgrade to dtc $(DTC_MIN_VERSION) or newer'; \
- false; \
- else \
- if [ -n "$(CONFIG_PYLIBFDT)" ]; then \
- if ! echo "import libfdt" | $(PYTHON3) 2>/dev/null; then \
- echo '*** pylibfdt does not seem to be available with $(PYTHON3)'; \
- false; \
- fi; \
- fi; \
- fi; \
- fi; \
- fi
+ $(MAKE) $(build)=scripts/dtc
# ---------------------------------------------------------------------------
quiet_cmd_cpp_lds = LDS $@