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mediatek: filogic: reorder mt7981 DT properties
Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
This commit is contained in:
Rafał Miłecki
parent
faa7b7dd0a
commit
388bc4b365
@ -27,17 +27,17 @@
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x0>;
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device_type = "cpu";
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enable-method = "psci";
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x1>;
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device_type = "cpu";
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enable-method = "psci";
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};
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};
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@ -50,9 +50,9 @@
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clk40m: oscillator@0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <40000000>;
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clock-output-names = "clkxtal";
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#clock-cells = <0>;
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};
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psci {
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@ -78,9 +78,9 @@
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};
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reserved-memory {
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ranges;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* 64 KiB reserved for ramoops/pstore */
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ramoops@42ff0000 {
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@ -119,13 +119,12 @@
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gic: interrupt-controller@c000000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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interrupt-controller;
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reg = <0 0x0c000000 0 0x40000>, /* GICD */
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<0 0x0c080000 0 0x200000>; /* GICR */
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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consys: consys@10000000 {
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@ -169,13 +168,13 @@
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pwm: pwm@10048000 {
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compatible = "mediatek,mt7981-pwm";
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reg = <0 0x10048000 0 0x1000>;
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#pwm-cells = <2>;
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clocks = <&infracfg CLK_INFRA_PWM_STA>,
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<&infracfg CLK_INFRA_PWM_HCK>,
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<&infracfg CLK_INFRA_PWM1_CK>,
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<&infracfg CLK_INFRA_PWM2_CK>,
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<&infracfg CLK_INFRA_PWM3_CK>;
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clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
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#pwm-cells = <2>;
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};
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sgmiisys0: syscon@10060000 {
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@ -285,8 +284,6 @@
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spi2: spi@11009000 {
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compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0x11009000 0 0x100>;
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interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&topckgen CLK_TOP_CB_M_D2>,
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@ -294,13 +291,13 @@
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<&infracfg CLK_INFRA_SPI2_CK>,
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<&infracfg CLK_INFRA_SPI2_HCK_CK>;
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clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi0: spi@1100a000 {
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compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0x1100a000 0 0x100>;
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&topckgen CLK_TOP_CB_M_D2>,
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@ -309,13 +306,13 @@
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<&infracfg CLK_INFRA_SPI0_HCK_CK>;
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clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi1: spi@1100b000 {
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compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0x1100b000 0 0x100>;
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interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&topckgen CLK_TOP_CB_M_D2>,
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@ -323,21 +320,23 @@
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<&infracfg CLK_INFRA_SPI1_CK>,
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<&infracfg CLK_INFRA_SPI1_HCK_CK>;
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clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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thermal: thermal@1100c800 {
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#thermal-sensor-cells = <1>;
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compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal";
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reg = <0 0x1100c800 0 0x800>;
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interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CLK_INFRA_THERM_CK>,
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<&infracfg CLK_INFRA_ADC_26M_CK>;
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clock-names = "therm", "auxadc";
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mediatek,auxadc = <&auxadc>;
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mediatek,apmixedsys = <&apmixedsys>;
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nvmem-cells = <&thermal_calibration>;
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nvmem-cell-names = "calibration-data";
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#thermal-sensor-cells = <1>;
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mediatek,auxadc = <&auxadc>;
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mediatek,apmixedsys = <&apmixedsys>;
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};
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auxadc: adc@1100d000 {
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@ -421,16 +420,13 @@
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pcie: pcie@11280000 {
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compatible = "mediatek,mt7981-pcie",
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"mediatek,mt7986-pcie";
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device_type = "pci";
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reg = <0 0x11280000 0 0x4000>;
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reg-names = "pcie-mac";
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#address-cells = <3>;
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#size-cells = <2>;
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interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0 0x20000000
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0x0 0x20000000 0 0x10000000>;
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status = "disabled";
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device_type = "pci";
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interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
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bus-range = <0x00 0xff>;
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clocks = <&infracfg CLK_INFRA_IPCIE_CK>,
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<&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
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@ -440,16 +436,19 @@
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phys = <&u3port0 PHY_TYPE_PCIE>;
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phy-names = "pcie-phy";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc 0>,
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<0 0 0 2 &pcie_intc 1>,
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<0 0 0 3 &pcie_intc 2>,
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<0 0 0 4 &pcie_intc 3>;
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#interrupt-cells = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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status = "disabled";
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pcie_intc: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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#address-cells = <0>;
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};
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};
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@ -528,9 +527,9 @@
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usb_phy: usb-phy@11e10000 {
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compatible = "mediatek,mt7981",
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"mediatek,generic-tphy-v2";
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ranges = <0 0 0x11e10000 0x1700>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0x11e10000 0x1700>;
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status = "disabled";
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u2port0: usb-phy@0 {
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@ -583,13 +582,13 @@
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};
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ethsys: syscon@15000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "mediatek,mt7981-ethsys",
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"syscon";
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reg = <0 0x15000000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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wed: wed@15010000 {
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@ -653,8 +652,8 @@
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#size-cells = <0>;
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int_gbe_phy: ethernet-phy@0 {
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reg = <0>;
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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phy-mode = "gmii";
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phy-is-integrated;
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nvmem-cells = <&phy_calibration>;
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@ -719,6 +718,9 @@
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wifi: wifi@18000000 {
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compatible = "mediatek,mt7981-wmac";
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reg = <0 0x18000000 0 0x1000000>,
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<0 0x10003000 0 0x1000>,
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<0 0x11d10000 0 0x1000>;
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resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
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reset-names = "consys";
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pinctrl-0 = <&wifi_dbdc_pins>;
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@ -726,9 +728,6 @@
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clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
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<&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
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clock-names = "mcu", "ap2conn";
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reg = <0 0x18000000 0 0x1000000>,
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<0 0x10003000 0 0x1000>,
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<0 0x11d10000 0 0x1000>;
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interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
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