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mediatek: filogic: reorder mt7981 DT SoC reg-based nodes
Follow upstream Linux kernel guidelines: https://www.kernel.org/doc/html/next/devicetree/bindings/dts-coding-style.html#order-of-nodes Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
This commit is contained in:
Rafał Miłecki
parent
c094131c1a
commit
faa7b7dd0a
@ -117,56 +117,21 @@
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#address-cells = <2>;
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#size-cells = <2>;
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pwm: pwm@10048000 {
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compatible = "mediatek,mt7981-pwm";
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reg = <0 0x10048000 0 0x1000>;
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#pwm-cells = <2>;
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clocks = <&infracfg CLK_INFRA_PWM_STA>,
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<&infracfg CLK_INFRA_PWM_HCK>,
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<&infracfg CLK_INFRA_PWM1_CK>,
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<&infracfg CLK_INFRA_PWM2_CK>,
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<&infracfg CLK_INFRA_PWM3_CK>;
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clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
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};
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thermal: thermal@1100c800 {
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#thermal-sensor-cells = <1>;
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compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal";
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reg = <0 0x1100c800 0 0x800>;
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interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CLK_INFRA_THERM_CK>,
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<&infracfg CLK_INFRA_ADC_26M_CK>;
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clock-names = "therm", "auxadc";
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mediatek,auxadc = <&auxadc>;
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mediatek,apmixedsys = <&apmixedsys>;
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nvmem-cells = <&thermal_calibration>;
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nvmem-cell-names = "calibration-data";
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};
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auxadc: adc@1100d000 {
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compatible = "mediatek,mt7981-auxadc",
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"mediatek,mt7986-auxadc",
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"mediatek,mt7622-auxadc";
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reg = <0 0x1100d000 0 0x1000>;
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clocks = <&infracfg CLK_INFRA_ADC_26M_CK>,
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<&infracfg CLK_INFRA_ADC_FRC_CK>;
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clock-names = "main", "32k";
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#io-channel-cells = <1>;
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};
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wdma: wdma@15104800 {
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compatible = "mediatek,wed-wdma";
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reg = <0 0x15104800 0 0x400>,
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<0 0x15104c00 0 0x400>;
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};
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ap2woccif: ap2woccif@151a5000 {
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compatible = "mediatek,ap2woccif";
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reg = <0 0x151a5000 0 0x1000>,
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<0 0x151ad000 0 0x1000>;
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gic: interrupt-controller@c000000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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reg = <0 0x0c000000 0 0x40000>, /* GICD */
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<0 0x0c080000 0 0x200000>; /* GICR */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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consys: consys@10000000 {
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compatible = "mediatek,mt7981-consys";
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reg = <0 0x10000000 0 0x8600000>;
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memory-region = <&wmcpu_emi>;
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};
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infracfg: infracfg@10001000 {
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@ -175,18 +140,17 @@
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#clock-cells = <1>;
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};
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wed_pcie: wed_pcie@10003000 {
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compatible = "mediatek,wed_pcie";
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reg = <0 0x10003000 0 0x10>;
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};
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topckgen: topckgen@1001B000 {
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compatible = "mediatek,mt7981-topckgen", "syscon";
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reg = <0 0x1001B000 0 0x1000>;
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#clock-cells = <1>;
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};
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apmixedsys: apmixedsys@1001E000 {
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compatible = "mediatek,mt7981-apmixedsys", "syscon";
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reg = <0 0x1001E000 0 0x1000>;
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#clock-cells = <1>;
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};
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watchdog: watchdog@1001c000 {
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compatible = "mediatek,mt7986-wdt",
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"mediatek,mt6589-wdt";
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@ -196,15 +160,49 @@
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status = "disabled";
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};
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gic: interrupt-controller@c000000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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interrupt-controller;
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reg = <0 0x0c000000 0 0x40000>, /* GICD */
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<0 0x0c080000 0 0x200000>; /* GICR */
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apmixedsys: apmixedsys@1001E000 {
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compatible = "mediatek,mt7981-apmixedsys", "syscon";
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reg = <0 0x1001E000 0 0x1000>;
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#clock-cells = <1>;
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};
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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pwm: pwm@10048000 {
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compatible = "mediatek,mt7981-pwm";
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reg = <0 0x10048000 0 0x1000>;
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#pwm-cells = <2>;
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clocks = <&infracfg CLK_INFRA_PWM_STA>,
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<&infracfg CLK_INFRA_PWM_HCK>,
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<&infracfg CLK_INFRA_PWM1_CK>,
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<&infracfg CLK_INFRA_PWM2_CK>,
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<&infracfg CLK_INFRA_PWM3_CK>;
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clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
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};
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sgmiisys0: syscon@10060000 {
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compatible = "mediatek,mt7981-sgmiisys_0", "syscon";
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reg = <0 0x10060000 0 0x1000>;
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mediatek,pnswap;
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#clock-cells = <1>;
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};
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sgmiisys1: syscon@10070000 {
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compatible = "mediatek,mt7981-sgmiisys_1", "syscon";
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reg = <0 0x10070000 0 0x1000>;
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#clock-cells = <1>;
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};
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crypto: crypto@10320000 {
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compatible = "inside-secure,safexcel-eip97";
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reg = <0 0x10320000 0 0x40000>;
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "ring0", "ring1", "ring2", "ring3";
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clocks = <&topckgen CLK_TOP_EIP97B>;
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clock-names = "top_eip97_ck";
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assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>;
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};
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uart0: serial@11002000 {
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@ -251,6 +249,24 @@
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status = "disabled";
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};
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snand: snfi@11005000 {
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compatible = "mediatek,mt7986-snand";
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reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>;
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reg-names = "nfi", "ecc";
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interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
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<&infracfg CLK_INFRA_NFI1_CK>,
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<&infracfg CLK_INFRA_NFI_HCK_CK>;
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clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
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assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
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<&topckgen CLK_TOP_NFI1X_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>,
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<&topckgen CLK_TOP_CB_M_D8>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c0: i2c@11007000 {
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compatible = "mediatek,mt7981-i2c";
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reg = <0 0x11007000 0 0x1000>,
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@ -267,6 +283,141 @@
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status = "disabled";
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};
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spi2: spi@11009000 {
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compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0x11009000 0 0x100>;
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interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&topckgen CLK_TOP_CB_M_D2>,
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<&topckgen CLK_TOP_SPI_SEL>,
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<&infracfg CLK_INFRA_SPI2_CK>,
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<&infracfg CLK_INFRA_SPI2_HCK_CK>;
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clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
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status = "disabled";
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};
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spi0: spi@1100a000 {
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compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0x1100a000 0 0x100>;
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interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&topckgen CLK_TOP_CB_M_D2>,
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<&topckgen CLK_TOP_SPI_SEL>,
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<&infracfg CLK_INFRA_SPI0_CK>,
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<&infracfg CLK_INFRA_SPI0_HCK_CK>;
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clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
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status = "disabled";
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};
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spi1: spi@1100b000 {
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compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0 0x1100b000 0 0x100>;
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interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&topckgen CLK_TOP_CB_M_D2>,
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<&topckgen CLK_TOP_SPIM_MST_SEL>,
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<&infracfg CLK_INFRA_SPI1_CK>,
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<&infracfg CLK_INFRA_SPI1_HCK_CK>;
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clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
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status = "disabled";
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};
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thermal: thermal@1100c800 {
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#thermal-sensor-cells = <1>;
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compatible = "mediatek,mt7981-thermal", "mediatek,mt7986-thermal";
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reg = <0 0x1100c800 0 0x800>;
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interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CLK_INFRA_THERM_CK>,
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<&infracfg CLK_INFRA_ADC_26M_CK>;
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clock-names = "therm", "auxadc";
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mediatek,auxadc = <&auxadc>;
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mediatek,apmixedsys = <&apmixedsys>;
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nvmem-cells = <&thermal_calibration>;
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nvmem-cell-names = "calibration-data";
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};
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auxadc: adc@1100d000 {
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compatible = "mediatek,mt7981-auxadc",
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"mediatek,mt7986-auxadc",
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"mediatek,mt7622-auxadc";
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reg = <0 0x1100d000 0 0x1000>;
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clocks = <&infracfg CLK_INFRA_ADC_26M_CK>,
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<&infracfg CLK_INFRA_ADC_FRC_CK>;
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clock-names = "main", "32k";
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#io-channel-cells = <1>;
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};
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xhci: usb@11200000 {
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compatible = "mediatek,mt7986-xhci",
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"mediatek,mtk-xhci";
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reg = <0 0x11200000 0 0x2e00>,
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<0 0x11203e00 0 0x0100>;
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reg-names = "mac", "ippc";
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interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
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<&infracfg CLK_INFRA_IUSB_CK>,
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<&infracfg CLK_INFRA_IUSB_133_CK>,
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<&infracfg CLK_INFRA_IUSB_66M_CK>,
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<&topckgen CLK_TOP_U2U3_XHCI_SEL>;
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clock-names = "sys_ck",
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"ref_ck",
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"mcu_ck",
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"dma_ck",
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"xhci_ck";
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phys = <&u2port0 PHY_TYPE_USB2>,
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<&u3port0 PHY_TYPE_USB3>;
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vusb33-supply = <®_3p3v>;
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status = "disabled";
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};
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afe: audio-controller@11210000 {
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compatible = "mediatek,mt79xx-audio";
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reg = <0 0x11210000 0 0x9000>;
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interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
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<&infracfg CLK_INFRA_AUD_26M_CK>,
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<&infracfg CLK_INFRA_AUD_L_CK>,
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<&infracfg CLK_INFRA_AUD_AUD_CK>,
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<&infracfg CLK_INFRA_AUD_EG2_CK>,
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<&topckgen CLK_TOP_AUD_SEL>;
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clock-names = "aud_bus_ck",
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"aud_26m_ck",
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"aud_l_ck",
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"aud_aud_ck",
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"aud_eg2_ck",
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"aud_sel";
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assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
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<&topckgen CLK_TOP_A1SYS_SEL>,
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<&topckgen CLK_TOP_AUD_L_SEL>,
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<&topckgen CLK_TOP_A_TUNER_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>,
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<&topckgen CLK_TOP_APLL2_D4>,
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<&topckgen CLK_TOP_CB_APLL2_196M>,
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<&topckgen CLK_TOP_APLL2_D4>;
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status = "disabled";
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};
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mmc0: mmc@11230000 {
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compatible = "mediatek,mt7986-mmc",
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"mediatek,mt7981-mmc";
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reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>;
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interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CLK_INFRA_MSDC_CK>,
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<&infracfg CLK_INFRA_MSDC_HCK_CK>,
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<&infracfg CLK_INFRA_MSDC_66M_CK>,
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<&infracfg CLK_INFRA_MSDC_133M_CK>;
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assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>,
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<&topckgen CLK_TOP_EMMC_400M_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
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<&topckgen CLK_TOP_CB_NET2_D2>;
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clock-names = "source", "hclk", "axi_cg", "ahb_cg";
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status = "disabled";
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};
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pcie: pcie@11280000 {
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compatible = "mediatek,mt7981-pcie",
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"mediatek,mt7986-pcie";
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@ -302,20 +453,6 @@
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};
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};
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crypto: crypto@10320000 {
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compatible = "inside-secure,safexcel-eip97";
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reg = <0 0x10320000 0 0x40000>;
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "ring0", "ring1", "ring2", "ring3";
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clocks = <&topckgen CLK_TOP_EIP97B>;
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clock-names = "top_eip97_ck";
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assigned-clocks = <&topckgen CLK_TOP_EIP97B_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_CB_NET1_D5>;
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};
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pio: pinctrl@11d00000 {
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compatible = "mediatek,mt7981-pinctrl";
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reg = <0 0x11d00000 0 0x1000>,
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@ -382,6 +519,69 @@
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};
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};
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topmisc: topmisc@11d10000 {
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compatible = "mediatek,mt7981-topmisc", "syscon";
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reg = <0 0x11d10000 0 0x10000>;
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#clock-cells = <1>;
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};
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usb_phy: usb-phy@11e10000 {
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compatible = "mediatek,mt7981",
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"mediatek,generic-tphy-v2";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0x11e10000 0x1700>;
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status = "disabled";
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u2port0: usb-phy@0 {
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reg = <0x0 0x700>;
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clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
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clock-names = "ref";
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#phy-cells = <1>;
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};
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u3port0: usb-phy@700 {
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reg = <0x700 0x900>;
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clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
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clock-names = "ref";
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#phy-cells = <1>;
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mediatek,syscon-type = <&topmisc 0x218 0>;
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status = "okay";
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};
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};
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efuse: efuse@11f20000 {
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compatible = "mediatek,mt7981-efuse",
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"mediatek,efuse";
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reg = <0 0x11f20000 0 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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status = "okay";
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thermal_calibration: thermal-calib@274 {
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reg = <0x274 0xc>;
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};
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phy_calibration: phy-calib@8dc {
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reg = <0x8dc 0x10>;
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};
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comb_rx_imp_p0: usb3-rx-imp@8c8 {
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reg = <0x8c8 1>;
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bits = <0 5>;
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};
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comb_tx_imp_p0: usb3-tx-imp@8c8 {
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reg = <0x8c8 2>;
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bits = <5 5>;
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};
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comb_intr_p0: usb3-intr@8c9 {
|
||||
reg = <0x8c9 1>;
|
||||
bits = <2 6>;
|
||||
};
|
||||
};
|
||||
|
||||
ethsys: syscon@15000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
@ -480,14 +680,10 @@
|
||||
};
|
||||
};
|
||||
|
||||
wo_dlm0: syscon@151e8000 {
|
||||
compatible = "mediatek,mt7986-wo-dlm", "syscon";
|
||||
reg = <0 0x151e8000 0 0x2000>;
|
||||
};
|
||||
|
||||
wo_ilm0: syscon@151e0000 {
|
||||
compatible = "mediatek,mt7986-wo-ilm", "syscon";
|
||||
reg = <0 0x151e0000 0 0x8000>;
|
||||
wdma: wdma@15104800 {
|
||||
compatible = "mediatek,wed-wdma";
|
||||
reg = <0 0x15104800 0 0x400>,
|
||||
<0 0x15104c00 0 0x400>;
|
||||
};
|
||||
|
||||
wo_cpuboot: syscon@15194000 {
|
||||
@ -495,6 +691,15 @@
|
||||
reg = <0 0x15194000 0 0x1000>;
|
||||
};
|
||||
|
||||
ap2woccif: ap2woccif@151a5000 {
|
||||
compatible = "mediatek,ap2woccif";
|
||||
reg = <0 0x151a5000 0 0x1000>,
|
||||
<0 0x151ad000 0 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
wo_ccif0: syscon@151a5000 {
|
||||
compatible = "mediatek,mt7986-wo-ccif", "syscon";
|
||||
reg = <0 0x151a5000 0 0x1000>;
|
||||
@ -502,219 +707,14 @@
|
||||
interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sgmiisys0: syscon@10060000 {
|
||||
compatible = "mediatek,mt7981-sgmiisys_0", "syscon";
|
||||
reg = <0 0x10060000 0 0x1000>;
|
||||
mediatek,pnswap;
|
||||
#clock-cells = <1>;
|
||||
wo_ilm0: syscon@151e0000 {
|
||||
compatible = "mediatek,mt7986-wo-ilm", "syscon";
|
||||
reg = <0 0x151e0000 0 0x8000>;
|
||||
};
|
||||
|
||||
sgmiisys1: syscon@10070000 {
|
||||
compatible = "mediatek,mt7981-sgmiisys_1", "syscon";
|
||||
reg = <0 0x10070000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
topmisc: topmisc@11d10000 {
|
||||
compatible = "mediatek,mt7981-topmisc", "syscon";
|
||||
reg = <0 0x11d10000 0 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
snand: snfi@11005000 {
|
||||
compatible = "mediatek,mt7986-snand";
|
||||
reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>;
|
||||
reg-names = "nfi", "ecc";
|
||||
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&infracfg CLK_INFRA_SPINFI1_CK>,
|
||||
<&infracfg CLK_INFRA_NFI1_CK>,
|
||||
<&infracfg CLK_INFRA_NFI_HCK_CK>;
|
||||
clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
|
||||
assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
|
||||
<&topckgen CLK_TOP_NFI1X_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D8>,
|
||||
<&topckgen CLK_TOP_CB_M_D8>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc0: mmc@11230000 {
|
||||
compatible = "mediatek,mt7986-mmc",
|
||||
"mediatek,mt7981-mmc";
|
||||
reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&infracfg CLK_INFRA_MSDC_CK>,
|
||||
<&infracfg CLK_INFRA_MSDC_HCK_CK>,
|
||||
<&infracfg CLK_INFRA_MSDC_66M_CK>,
|
||||
<&infracfg CLK_INFRA_MSDC_133M_CK>;
|
||||
assigned-clocks = <&topckgen CLK_TOP_EMMC_208M_SEL>,
|
||||
<&topckgen CLK_TOP_EMMC_400M_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_CB_M_D2>,
|
||||
<&topckgen CLK_TOP_CB_NET2_D2>;
|
||||
clock-names = "source", "hclk", "axi_cg", "ahb_cg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wed_pcie: wed_pcie@10003000 {
|
||||
compatible = "mediatek,wed_pcie";
|
||||
reg = <0 0x10003000 0 0x10>;
|
||||
};
|
||||
|
||||
spi0: spi@1100a000 {
|
||||
compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0 0x1100a000 0 0x100>;
|
||||
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&topckgen CLK_TOP_CB_M_D2>,
|
||||
<&topckgen CLK_TOP_SPI_SEL>,
|
||||
<&infracfg CLK_INFRA_SPI0_CK>,
|
||||
<&infracfg CLK_INFRA_SPI0_HCK_CK>;
|
||||
|
||||
clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@1100b000 {
|
||||
compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0 0x1100b000 0 0x100>;
|
||||
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&topckgen CLK_TOP_CB_M_D2>,
|
||||
<&topckgen CLK_TOP_SPIM_MST_SEL>,
|
||||
<&infracfg CLK_INFRA_SPI1_CK>,
|
||||
<&infracfg CLK_INFRA_SPI1_HCK_CK>;
|
||||
clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi2: spi@11009000 {
|
||||
compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0 0x11009000 0 0x100>;
|
||||
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&topckgen CLK_TOP_CB_M_D2>,
|
||||
<&topckgen CLK_TOP_SPI_SEL>,
|
||||
<&infracfg CLK_INFRA_SPI2_CK>,
|
||||
<&infracfg CLK_INFRA_SPI2_HCK_CK>;
|
||||
clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
consys: consys@10000000 {
|
||||
compatible = "mediatek,mt7981-consys";
|
||||
reg = <0 0x10000000 0 0x8600000>;
|
||||
memory-region = <&wmcpu_emi>;
|
||||
};
|
||||
|
||||
xhci: usb@11200000 {
|
||||
compatible = "mediatek,mt7986-xhci",
|
||||
"mediatek,mtk-xhci";
|
||||
reg = <0 0x11200000 0 0x2e00>,
|
||||
<0 0x11203e00 0 0x0100>;
|
||||
reg-names = "mac", "ippc";
|
||||
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
|
||||
<&infracfg CLK_INFRA_IUSB_CK>,
|
||||
<&infracfg CLK_INFRA_IUSB_133_CK>,
|
||||
<&infracfg CLK_INFRA_IUSB_66M_CK>,
|
||||
<&topckgen CLK_TOP_U2U3_XHCI_SEL>;
|
||||
clock-names = "sys_ck",
|
||||
"ref_ck",
|
||||
"mcu_ck",
|
||||
"dma_ck",
|
||||
"xhci_ck";
|
||||
phys = <&u2port0 PHY_TYPE_USB2>,
|
||||
<&u3port0 PHY_TYPE_USB3>;
|
||||
vusb33-supply = <®_3p3v>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb_phy: usb-phy@11e10000 {
|
||||
compatible = "mediatek,mt7981",
|
||||
"mediatek,generic-tphy-v2";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x11e10000 0x1700>;
|
||||
status = "disabled";
|
||||
|
||||
u2port0: usb-phy@0 {
|
||||
reg = <0x0 0x700>;
|
||||
clocks = <&topckgen CLK_TOP_USB_FRMCNT_SEL>;
|
||||
clock-names = "ref";
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
u3port0: usb-phy@700 {
|
||||
reg = <0x700 0x900>;
|
||||
clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
|
||||
clock-names = "ref";
|
||||
#phy-cells = <1>;
|
||||
mediatek,syscon-type = <&topmisc 0x218 0>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
efuse: efuse@11f20000 {
|
||||
compatible = "mediatek,mt7981-efuse",
|
||||
"mediatek,efuse";
|
||||
reg = <0 0x11f20000 0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
status = "okay";
|
||||
|
||||
thermal_calibration: thermal-calib@274 {
|
||||
reg = <0x274 0xc>;
|
||||
};
|
||||
|
||||
phy_calibration: phy-calib@8dc {
|
||||
reg = <0x8dc 0x10>;
|
||||
};
|
||||
|
||||
comb_rx_imp_p0: usb3-rx-imp@8c8 {
|
||||
reg = <0x8c8 1>;
|
||||
bits = <0 5>;
|
||||
};
|
||||
|
||||
comb_tx_imp_p0: usb3-tx-imp@8c8 {
|
||||
reg = <0x8c8 2>;
|
||||
bits = <5 5>;
|
||||
};
|
||||
|
||||
comb_intr_p0: usb3-intr@8c9 {
|
||||
reg = <0x8c9 1>;
|
||||
bits = <2 6>;
|
||||
};
|
||||
};
|
||||
|
||||
afe: audio-controller@11210000 {
|
||||
compatible = "mediatek,mt79xx-audio";
|
||||
reg = <0 0x11210000 0 0x9000>;
|
||||
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&infracfg CLK_INFRA_AUD_BUS_CK>,
|
||||
<&infracfg CLK_INFRA_AUD_26M_CK>,
|
||||
<&infracfg CLK_INFRA_AUD_L_CK>,
|
||||
<&infracfg CLK_INFRA_AUD_AUD_CK>,
|
||||
<&infracfg CLK_INFRA_AUD_EG2_CK>,
|
||||
<&topckgen CLK_TOP_AUD_SEL>;
|
||||
clock-names = "aud_bus_ck",
|
||||
"aud_26m_ck",
|
||||
"aud_l_ck",
|
||||
"aud_aud_ck",
|
||||
"aud_eg2_ck",
|
||||
"aud_sel";
|
||||
assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
|
||||
<&topckgen CLK_TOP_A1SYS_SEL>,
|
||||
<&topckgen CLK_TOP_AUD_L_SEL>,
|
||||
<&topckgen CLK_TOP_A_TUNER_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_CB_APLL2_196M>,
|
||||
<&topckgen CLK_TOP_APLL2_D4>,
|
||||
<&topckgen CLK_TOP_CB_APLL2_196M>,
|
||||
<&topckgen CLK_TOP_APLL2_D4>;
|
||||
status = "disabled";
|
||||
wo_dlm0: syscon@151e8000 {
|
||||
compatible = "mediatek,mt7986-wo-dlm", "syscon";
|
||||
reg = <0 0x151e8000 0 0x2000>;
|
||||
};
|
||||
|
||||
wifi: wifi@18000000 {
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user