2021-02-27 23:12:21 +00:00
|
|
|
CONFIG_ARCH_32BIT_OFF_T=y
|
|
|
|
|
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
|
|
|
|
|
CONFIG_ARCH_MMAP_RND_BITS_MAX=15
|
|
|
|
|
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
|
2021-03-30 22:59:50 +00:00
|
|
|
CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED=y
|
2021-02-27 23:12:21 +00:00
|
|
|
CONFIG_ARCH_SUSPEND_POSSIBLE=y
|
|
|
|
|
CONFIG_AT803X_PHY=y
|
|
|
|
|
CONFIG_BLK_MQ_PCI=y
|
|
|
|
|
CONFIG_BOARD_SCACHE=y
|
|
|
|
|
CONFIG_BOUNCE=y
|
|
|
|
|
CONFIG_CEVT_R4K=y
|
|
|
|
|
CONFIG_CLKDEV_LOOKUP=y
|
|
|
|
|
CONFIG_CLKSRC_MIPS_GIC=y
|
2021-02-28 07:17:47 +00:00
|
|
|
CONFIG_CLOCKSOURCE_WATCHDOG=y
|
2021-02-27 23:12:21 +00:00
|
|
|
CONFIG_CLONE_BACKWARDS=y
|
|
|
|
|
CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
|
|
|
|
|
CONFIG_CMDLINE_BOOL=y
|
|
|
|
|
# CONFIG_CMDLINE_OVERRIDE is not set
|
|
|
|
|
CONFIG_COMMON_CLK=y
|
|
|
|
|
# CONFIG_COMMON_CLK_BOSTON is not set
|
|
|
|
|
CONFIG_COMPAT_32BIT_TIME=y
|
|
|
|
|
CONFIG_CPU_GENERIC_DUMP_TLB=y
|
2021-02-28 07:17:47 +00:00
|
|
|
CONFIG_CPU_HAS_DIEI=y
|
2021-02-27 23:12:21 +00:00
|
|
|
CONFIG_CPU_HAS_PREFETCH=y
|
|
|
|
|
CONFIG_CPU_HAS_RIXI=y
|
|
|
|
|
CONFIG_CPU_HAS_SYNC=y
|
2021-03-30 22:59:50 +00:00
|
|
|
CONFIG_CPU_IDLE=y
|
|
|
|
|
CONFIG_CPU_IDLE_GOV_TEO=y
|
2021-02-27 23:12:21 +00:00
|
|
|
CONFIG_CPU_MIPS32=y
|
|
|
|
|
# CONFIG_CPU_MIPS32_R1 is not set
|
|
|
|
|
CONFIG_CPU_MIPS32_R2=y
|
|
|
|
|
CONFIG_CPU_MIPSR2=y
|
|
|
|
|
CONFIG_CPU_MIPSR2_IRQ_EI=y
|
|
|
|
|
CONFIG_CPU_MIPSR2_IRQ_VI=y
|
|
|
|
|
CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
|
2021-03-30 22:59:50 +00:00
|
|
|
CONFIG_CPU_PM=y
|
2021-02-27 23:12:21 +00:00
|
|
|
CONFIG_CPU_R4K_CACHE_TLB=y
|
|
|
|
|
CONFIG_CPU_RMAP=y
|
|
|
|
|
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
|
|
|
|
|
CONFIG_CPU_SUPPORTS_HIGHMEM=y
|
|
|
|
|
CONFIG_CPU_SUPPORTS_MSA=y
|
|
|
|
|
CONFIG_CRC16=y
|
2022-06-20 12:49:45 +00:00
|
|
|
CONFIG_CRYPTO_BLAKE2S=y
|
2021-02-27 23:12:21 +00:00
|
|
|
CONFIG_CRYPTO_DEFLATE=y
|
|
|
|
|
CONFIG_CRYPTO_HASH_INFO=y
|
2022-06-20 12:49:45 +00:00
|
|
|
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
|
2021-02-27 23:12:21 +00:00
|
|
|
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
|
|
|
|
|
CONFIG_CRYPTO_LZO=y
|
|
|
|
|
CONFIG_CRYPTO_RNG2=y
|
|
|
|
|
CONFIG_CSRC_R4K=y
|
|
|
|
|
CONFIG_DEBUG_PINCTRL=y
|
|
|
|
|
CONFIG_DIMLIB=y
|
|
|
|
|
CONFIG_DMA_NONCOHERENT=y
|
|
|
|
|
# CONFIG_DTB_GNUBEE1 is not set
|
|
|
|
|
# CONFIG_DTB_GNUBEE2 is not set
|
|
|
|
|
CONFIG_DTB_RT_NONE=y
|
|
|
|
|
CONFIG_DTC=y
|
|
|
|
|
CONFIG_EARLY_PRINTK=y
|
|
|
|
|
CONFIG_FIXED_PHY=y
|
|
|
|
|
CONFIG_FW_LOADER_PAGED_BUF=y
|
|
|
|
|
CONFIG_GENERIC_ATOMIC64=y
|
|
|
|
|
CONFIG_GENERIC_CLOCKEVENTS=y
|
|
|
|
|
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
|
|
|
|
|
CONFIG_GENERIC_CMOS_UPDATE=y
|
|
|
|
|
CONFIG_GENERIC_CPU_AUTOPROBE=y
|
|
|
|
|
CONFIG_GENERIC_GETTIMEOFDAY=y
|
|
|
|
|
CONFIG_GENERIC_IOMAP=y
|
|
|
|
|
CONFIG_GENERIC_IRQ_CHIP=y
|
|
|
|
|
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
|
|
|
|
|
CONFIG_GENERIC_IRQ_SHOW=y
|
|
|
|
|
CONFIG_GENERIC_LIB_ASHLDI3=y
|
|
|
|
|
CONFIG_GENERIC_LIB_ASHRDI3=y
|
|
|
|
|
CONFIG_GENERIC_LIB_CMPDI2=y
|
|
|
|
|
CONFIG_GENERIC_LIB_LSHRDI3=y
|
|
|
|
|
CONFIG_GENERIC_LIB_UCMPDI2=y
|
|
|
|
|
CONFIG_GENERIC_PCI_IOMAP=y
|
|
|
|
|
CONFIG_GENERIC_PHY=y
|
|
|
|
|
CONFIG_GENERIC_PINCONF=y
|
|
|
|
|
CONFIG_GENERIC_SCHED_CLOCK=y
|
|
|
|
|
CONFIG_GENERIC_SMP_IDLE_THREAD=y
|
|
|
|
|
CONFIG_GENERIC_TIME_VSYSCALL=y
|
2021-02-28 07:17:47 +00:00
|
|
|
CONFIG_GLOB=y
|
2021-02-27 23:12:21 +00:00
|
|
|
CONFIG_GPIOLIB=y
|
|
|
|
|
CONFIG_GPIOLIB_IRQCHIP=y
|
|
|
|
|
CONFIG_GPIO_GENERIC=y
|
|
|
|
|
CONFIG_GPIO_MT7621=y
|
|
|
|
|
# CONFIG_GPIO_RALINK is not set
|
|
|
|
|
CONFIG_GPIO_WATCHDOG=y
|
|
|
|
|
# CONFIG_GPIO_WATCHDOG_ARCH_INITCALL is not set
|
|
|
|
|
CONFIG_GRO_CELLS=y
|
|
|
|
|
CONFIG_HANDLE_DOMAIN_IRQ=y
|
|
|
|
|
CONFIG_HARDWARE_WATCHPOINTS=y
|
|
|
|
|
CONFIG_HAS_DMA=y
|
|
|
|
|
CONFIG_HAS_IOMEM=y
|
|
|
|
|
CONFIG_HAS_IOPORT_MAP=y
|
|
|
|
|
CONFIG_HIGHMEM=y
|
|
|
|
|
CONFIG_I2C=y
|
|
|
|
|
CONFIG_I2C_BOARDINFO=y
|
2022-01-28 16:56:34 +00:00
|
|
|
CONFIG_I2C_CHARDEV=y
|
2021-05-06 16:07:18 +00:00
|
|
|
CONFIG_I2C_GPIO=y
|
2021-02-27 23:12:21 +00:00
|
|
|
CONFIG_I2C_MT7621=y
|
|
|
|
|
CONFIG_INITRAMFS_SOURCE=""
|
|
|
|
|
CONFIG_IRQCHIP=y
|
|
|
|
|
CONFIG_IRQ_DOMAIN=y
|
|
|
|
|
CONFIG_IRQ_DOMAIN_HIERARCHY=y
|
|
|
|
|
CONFIG_IRQ_FORCED_THREADING=y
|
|
|
|
|
CONFIG_IRQ_MIPS_CPU=y
|
|
|
|
|
CONFIG_IRQ_WORK=y
|
|
|
|
|
CONFIG_LED_TRIGGER_PHY=y
|
|
|
|
|
CONFIG_LIBFDT=y
|
|
|
|
|
CONFIG_LOCK_DEBUGGING_SUPPORT=y
|
|
|
|
|
CONFIG_LZO_COMPRESS=y
|
|
|
|
|
CONFIG_LZO_DECOMPRESS=y
|
|
|
|
|
CONFIG_MDIO_BUS=y
|
|
|
|
|
CONFIG_MDIO_DEVICE=y
|
2022-02-03 12:07:04 +00:00
|
|
|
CONFIG_MEDIATEK_GE_PHY=y
|
2021-02-27 23:12:21 +00:00
|
|
|
CONFIG_MEMFD_CREATE=y
|
|
|
|
|
CONFIG_MFD_SYSCON=y
|
|
|
|
|
CONFIG_MIGRATION=y
|
|
|
|
|
CONFIG_MIKROTIK=y
|
|
|
|
|
CONFIG_MIKROTIK_RB_SYSFS=y
|
|
|
|
|
CONFIG_MIPS=y
|
|
|
|
|
CONFIG_MIPS_ASID_BITS=8
|
|
|
|
|
CONFIG_MIPS_ASID_SHIFT=0
|
|
|
|
|
CONFIG_MIPS_CBPF_JIT=y
|
|
|
|
|
CONFIG_MIPS_CLOCK_VSYSCALL=y
|
|
|
|
|
CONFIG_MIPS_CM=y
|
|
|
|
|
# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
|
|
|
|
|
# CONFIG_MIPS_CMDLINE_DTB_EXTEND is not set
|
|
|
|
|
# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
|
|
|
|
|
CONFIG_MIPS_CMDLINE_FROM_DTB=y
|
|
|
|
|
CONFIG_MIPS_CPC=y
|
|
|
|
|
CONFIG_MIPS_CPS=y
|
2021-03-30 22:59:50 +00:00
|
|
|
CONFIG_MIPS_CPS_CPUIDLE=y
|
2021-02-27 23:12:21 +00:00
|
|
|
# CONFIG_MIPS_CPS_NS16550_BOOL is not set
|
2021-03-30 22:59:50 +00:00
|
|
|
CONFIG_MIPS_CPS_PM=y
|
2021-02-27 23:12:21 +00:00
|
|
|
CONFIG_MIPS_CPU_SCACHE=y
|
|
|
|
|
# CONFIG_MIPS_ELF_APPENDED_DTB is not set
|
|
|
|
|
CONFIG_MIPS_GIC=y
|
|
|
|
|
CONFIG_MIPS_L1_CACHE_SHIFT=5
|
2021-02-28 07:17:47 +00:00
|
|
|
CONFIG_MIPS_LD_CAN_LINK_VDSO=y
|
2021-02-27 23:12:21 +00:00
|
|
|
CONFIG_MIPS_MT=y
|
|
|
|
|
CONFIG_MIPS_MT_FPAFF=y
|
|
|
|
|
CONFIG_MIPS_MT_SMP=y
|
|
|
|
|
# CONFIG_MIPS_NO_APPENDED_DTB is not set
|
|
|
|
|
CONFIG_MIPS_NR_CPU_NR_MAP=4
|
|
|
|
|
CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
|
|
|
|
|
CONFIG_MIPS_RAW_APPENDED_DTB=y
|
|
|
|
|
CONFIG_MIPS_SPRAM=y
|
|
|
|
|
CONFIG_MODULES_USE_ELF_REL=y
|
|
|
|
|
CONFIG_MT7621_WDT=y
|
|
|
|
|
# CONFIG_MTD_CFI_INTELEXT is not set
|
|
|
|
|
CONFIG_MTD_CMDLINE_PARTS=y
|
|
|
|
|
CONFIG_MTD_NAND_CORE=y
|
2021-02-28 07:17:47 +00:00
|
|
|
CONFIG_MTD_NAND_ECC=y
|
2021-02-27 23:12:21 +00:00
|
|
|
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
|
|
|
|
|
CONFIG_MTD_NAND_MT7621=y
|
2022-01-13 17:32:26 +00:00
|
|
|
CONFIG_MTD_NAND_MTK_BMT=y
|
2021-02-27 23:12:21 +00:00
|
|
|
CONFIG_MTD_PHYSMAP=y
|
|
|
|
|
CONFIG_MTD_RAW_NAND=y
|
|
|
|
|
CONFIG_MTD_ROUTERBOOT_PARTS=y
|
ramips: add support for Beeline SmartBox GIGA
Beeline SmartBox GIGA is a wireless WiFi 5 router manufactured by
Sercomm company.
Device specification
--------------------
SoC Type: MediaTek MT7621AT
RAM: 256 MiB, Nanya NT5CC128M16JR-EK
Flash: 128 MiB, Macronix MX30LF1G18AC
Wireless 2.4 GHz (MT7603EN): b/g/n, 2x2
Wireless 5 GHz (MT7613BE): a/n/ac, 2x2
Ethernet: 3 ports - 2xGbE (WAN, LAN1), 1xFE (LAN2)
USB ports: 1xUSB3.0
Button: 1 button (Reset/WPS)
PCB ID: DBE00B-1.6MM
LEDs: 1 RGB LED
Power: 12 VDC, 1.5 A
Connector type: barrel
Bootloader: U-Boot
Installation
-----------------
1. Downgrade stock (Beeline) firmware to v.1.0.02;
2. Give factory OpenWrt image a shorter name, e.g. 1001.img;
3. Upload and update the firmware via the original web interface.
Remark: You might need make the 3rd step twice if your running firmware
is booted from the Slot 1 (Sercomm0 bootflag). The stock firmware
reverses the bootflag (Sercomm0 / Sercomm1) on each firmware update.
Revert to stock
---------------
1. Change the bootflag to Sercomm1 in OpenWrt CLI and then reboot:
printf 1 | dd bs=1 seek=7 count=1 of=/dev/mtdblock3
2. Optional: Update with any stock (Beeline) firmware if you want to
overwrite OpenWrt in Slot 0 completely.
MAC Addresses
-------------
+-----+-----------+---------+
| use | address | example |
+-----+-----------+---------+
| LAN | label | *:16 |
| WAN | label + 1 | *:17 |
| 2g | label + 4 | *:1a |
| 5g | label + 5 | *:1b |
+-----+-----------+---------+
The label MAC address was found in Factory 0x21000
Notes
-----
1. The following scripts are required for the build:
sercomm-crypto.py - already exists in OpenWrt
sercomm-partition-tag.py - already exists in OpenWrt
sercomm-payload.py - already exists in OpenWrt
sercomm-pid.py - new, the part of this pull request
sercomm-kernel-header.py - new, the part of this pull request
2. This device (same as other Sercomm S2,S3-based devices) requires
special LZMA and LOADADDR settings for successful boot:
LZMA_TEXT_START=0x82800000
KERNEL_LOADADDR=0x81001000
LOADADDR=0x80001000
3. This device (same as several other Sercomm-based devices - Beeline,
Netgear, Etisalat, Rostelecom) has partition map (mtd1) containing
real partition offsets, which may differ from device to device
depending on the number and location of bad blocks on NAND.
"fixed-partitions" is used if the partition map is not found or
corrupted. This behavour (it's the same as on stock firmware) is
provided by MTD_SERCOMM_PARTS module.
Signed-off-by: Mikhail Zhilkin <csharper2005@gmail.com>
2022-03-18 18:09:45 +00:00
|
|
|
CONFIG_MTD_SERCOMM_PARTS=y
|
2021-02-27 23:12:21 +00:00
|
|
|
CONFIG_MTD_SPI_NOR=y
|
2021-12-21 07:46:00 +00:00
|
|
|
CONFIG_MTD_SPI_NOR_USE_VARIABLE_ERASE=y
|
2021-02-27 23:12:21 +00:00
|
|
|
CONFIG_MTD_SPLIT_FIT_FW=y
|
|
|
|
|
CONFIG_MTD_SPLIT_MINOR_FW=y
|
|
|
|
|
CONFIG_MTD_SPLIT_SEAMA_FW=y
|
|
|
|
|
CONFIG_MTD_SPLIT_TPLINK_FW=y
|
|
|
|
|
CONFIG_MTD_SPLIT_TRX_FW=y
|
|
|
|
|
CONFIG_MTD_SPLIT_UIMAGE_FW=y
|
|
|
|
|
CONFIG_MTD_UBI=y
|
|
|
|
|
CONFIG_MTD_UBI_BEB_LIMIT=20
|
|
|
|
|
CONFIG_MTD_UBI_BLOCK=y
|
|
|
|
|
CONFIG_MTD_UBI_WL_THRESHOLD=4096
|
|
|
|
|
CONFIG_MTD_VIRT_CONCAT=y
|
|
|
|
|
# CONFIG_MTK_HSDMA is not set
|
|
|
|
|
CONFIG_NEED_DMA_MAP_STATE=y
|
|
|
|
|
CONFIG_NET_DEVLINK=y
|
|
|
|
|
CONFIG_NET_DSA=y
|
|
|
|
|
CONFIG_NET_DSA_MT7530=y
|
|
|
|
|
CONFIG_NET_DSA_TAG_MTK=y
|
|
|
|
|
CONFIG_NET_FLOW_LIMIT=y
|
|
|
|
|
CONFIG_NET_MEDIATEK_SOC=y
|
|
|
|
|
CONFIG_NET_SWITCHDEV=y
|
|
|
|
|
CONFIG_NET_VENDOR_MEDIATEK=y
|
|
|
|
|
# CONFIG_NET_VENDOR_RALINK is not set
|
2021-03-30 22:59:50 +00:00
|
|
|
CONFIG_NO_HZ_COMMON=y
|
|
|
|
|
CONFIG_NO_HZ_IDLE=y
|
2021-02-27 23:12:21 +00:00
|
|
|
CONFIG_NR_CPUS=4
|
2021-07-21 08:28:50 +00:00
|
|
|
CONFIG_NVMEM=y
|
2021-02-27 23:12:21 +00:00
|
|
|
CONFIG_OF=y
|
|
|
|
|
CONFIG_OF_ADDRESS=y
|
|
|
|
|
CONFIG_OF_EARLY_FLATTREE=y
|
|
|
|
|
CONFIG_OF_FLATTREE=y
|
|
|
|
|
CONFIG_OF_GPIO=y
|
|
|
|
|
CONFIG_OF_IRQ=y
|
|
|
|
|
CONFIG_OF_KOBJ=y
|
|
|
|
|
CONFIG_OF_MDIO=y
|
|
|
|
|
CONFIG_OF_NET=y
|
|
|
|
|
CONFIG_PADATA=y
|
|
|
|
|
CONFIG_PCI=y
|
|
|
|
|
CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
|
|
|
|
|
CONFIG_PCI_DOMAINS=y
|
|
|
|
|
CONFIG_PCI_DOMAINS_GENERIC=y
|
|
|
|
|
CONFIG_PCI_DRIVERS_GENERIC=y
|
|
|
|
|
CONFIG_PCI_MT7621=y
|
|
|
|
|
CONFIG_PCI_MT7621_PHY=y
|
|
|
|
|
CONFIG_PERF_USE_VMALLOC=y
|
|
|
|
|
CONFIG_PGTABLE_LEVELS=2
|
|
|
|
|
CONFIG_PHYLIB=y
|
|
|
|
|
CONFIG_PHYLINK=y
|
|
|
|
|
# CONFIG_PHY_RALINK_USB is not set
|
|
|
|
|
CONFIG_PINCTRL=y
|
2021-05-06 22:35:16 +00:00
|
|
|
CONFIG_PINCTRL_AW9523=y
|
2021-02-27 23:12:21 +00:00
|
|
|
CONFIG_PINCTRL_RT2880=y
|
|
|
|
|
# CONFIG_PINCTRL_SINGLE is not set
|
|
|
|
|
CONFIG_PINCTRL_SX150X=y
|
|
|
|
|
CONFIG_POWER_RESET=y
|
|
|
|
|
CONFIG_POWER_RESET_GPIO=y
|
|
|
|
|
CONFIG_POWER_SUPPLY=y
|
|
|
|
|
CONFIG_QUEUED_RWLOCKS=y
|
|
|
|
|
CONFIG_QUEUED_SPINLOCKS=y
|
|
|
|
|
CONFIG_RALINK=y
|
|
|
|
|
# CONFIG_RALINK_WDT is not set
|
|
|
|
|
CONFIG_RATIONAL=y
|
|
|
|
|
CONFIG_REGMAP=y
|
|
|
|
|
CONFIG_REGMAP_MMIO=y
|
|
|
|
|
CONFIG_REGULATOR=y
|
|
|
|
|
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
|
|
|
|
CONFIG_RESET_CONTROLLER=y
|
|
|
|
|
CONFIG_RFS_ACCEL=y
|
|
|
|
|
CONFIG_RPS=y
|
|
|
|
|
CONFIG_RTC_CLASS=y
|
|
|
|
|
CONFIG_RTC_DRV_BQ32K=y
|
|
|
|
|
CONFIG_RTC_DRV_PCF8563=y
|
|
|
|
|
CONFIG_RTC_I2C_AND_SPI=y
|
|
|
|
|
CONFIG_RTC_MC146818_LIB=y
|
|
|
|
|
CONFIG_SCHED_SMT=y
|
|
|
|
|
CONFIG_SERIAL_8250_NR_UARTS=3
|
|
|
|
|
CONFIG_SERIAL_8250_RUNTIME_UARTS=3
|
|
|
|
|
CONFIG_SERIAL_MCTRL_GPIO=y
|
|
|
|
|
CONFIG_SERIAL_OF_PLATFORM=y
|
|
|
|
|
CONFIG_SGL_ALLOC=y
|
|
|
|
|
CONFIG_SMP=y
|
|
|
|
|
CONFIG_SMP_UP=y
|
2021-02-28 07:17:47 +00:00
|
|
|
CONFIG_SOC_BUS=y
|
2021-02-27 23:12:21 +00:00
|
|
|
# CONFIG_SOC_MT7620 is not set
|
|
|
|
|
CONFIG_SOC_MT7621=y
|
|
|
|
|
# CONFIG_SOC_RT288X is not set
|
|
|
|
|
# CONFIG_SOC_RT305X is not set
|
|
|
|
|
# CONFIG_SOC_RT3883 is not set
|
|
|
|
|
CONFIG_SPI=y
|
|
|
|
|
CONFIG_SPI_MASTER=y
|
|
|
|
|
CONFIG_SPI_MEM=y
|
|
|
|
|
CONFIG_SPI_MT7621=y
|
|
|
|
|
# CONFIG_SPI_RT2880 is not set
|
|
|
|
|
CONFIG_SRCU=y
|
|
|
|
|
CONFIG_SWPHY=y
|
|
|
|
|
CONFIG_SYNC_R4K=y
|
|
|
|
|
CONFIG_SYSCTL_EXCEPTION_TRACE=y
|
|
|
|
|
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
|
|
|
|
|
CONFIG_SYS_HAS_CPU_MIPS32_R2=y
|
|
|
|
|
CONFIG_SYS_HAS_EARLY_PRINTK=y
|
|
|
|
|
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
|
|
|
|
|
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
|
|
|
|
|
CONFIG_SYS_SUPPORTS_HIGHMEM=y
|
|
|
|
|
CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y
|
|
|
|
|
CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
|
|
|
|
|
CONFIG_SYS_SUPPORTS_MIPS16=y
|
|
|
|
|
CONFIG_SYS_SUPPORTS_MIPS_CPS=y
|
|
|
|
|
CONFIG_SYS_SUPPORTS_MULTITHREADING=y
|
|
|
|
|
CONFIG_SYS_SUPPORTS_SCHED_SMT=y
|
|
|
|
|
CONFIG_SYS_SUPPORTS_SMP=y
|
|
|
|
|
CONFIG_SYS_SUPPORTS_ZBOOT=y
|
|
|
|
|
CONFIG_TARGET_ISA_REV=2
|
|
|
|
|
CONFIG_TICK_CPU_ACCOUNTING=y
|
|
|
|
|
CONFIG_TIMER_OF=y
|
|
|
|
|
CONFIG_TIMER_PROBE=y
|
|
|
|
|
CONFIG_TREE_RCU=y
|
|
|
|
|
CONFIG_TREE_SRCU=y
|
|
|
|
|
CONFIG_UBIFS_FS=y
|
|
|
|
|
CONFIG_USB_SUPPORT=y
|
|
|
|
|
CONFIG_USE_OF=y
|
|
|
|
|
CONFIG_WATCHDOG_CORE=y
|
|
|
|
|
CONFIG_WEAK_ORDERING=y
|
|
|
|
|
CONFIG_WEAK_REORDERING_BEYOND_LLSC=y
|
|
|
|
|
CONFIG_XPS=y
|
|
|
|
|
CONFIG_ZLIB_DEFLATE=y
|
|
|
|
|
CONFIG_ZLIB_INFLATE=y
|
