openwrt/target/linux/ramips/dts/mt7620a_lava_lr-25g001.dts

#include "mt7620a.dtsi"

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/mtd/partitions/uimage.h>

/ {
	compatible = "lava,lr-25g001", "ralink,mt7620a-soc";
	model = "LAVA LR-25G001";

	aliases {
		led-boot = &led_status;
		led-failsafe = &led_status;
		led-running = &led_status;
		led-upgrade = &led_status;
	};

	keys {
		compatible = "gpio-keys";

		wps {
			label = "wps";
			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_WPS_BUTTON>;
		};

		reset {
			label = "reset";
			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_RESTART>;
		};
	};

	leds {
		compatible = "gpio-leds";

		led_status: status {
			function = LED_FUNCTION_STATUS;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
		};

		wifi2g {
			label = "green:wifi2g";
			gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "phy1tpt";
		};

		wifi5g {
			label = "green:wifi5g";
			gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
			linux,default-trigger = "phy0tpt";
		};
	};

	gpio_export {
		compatible = "gpio-export";
		#size-cells = <0>;

		usbpower {
			gpio-export,name = "usbpower";
			gpio-export,output = <1>;
			gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
		};
	};
};

&spi0 {
	status = "okay";

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <10000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "jboot";
				reg = <0x0 0x10000>;
				read-only;
			};

			partition@10000 {
				compatible = "openwrt,uimage", "denx,uimage";
				openwrt,ih-magic = <IH_MAGIC_OKLI>;
				openwrt,offset = <0x10000>;
				label = "firmware";
				reg = <0x10000 0xfe0000>;
			};

			config: partition@ff0000 {
				label = "config";
				reg = <0xff0000 0x10000>;
				read-only;

				nvmem-layout {
					compatible = "fixed-layout";
					#address-cells = <1>;
					#size-cells = <1>;

					eeprom_config_e08a: eeprom@e08a {
						reg = <0xe08a 0x200>;
					};

					macaddr_config_e07e: macaddr@e07e {
						compatible = "mac-base";
						reg = <0xe07e 0x6>;
						#nvmem-cell-cells = <1>;
					};
				};
			};
		};
	};
};

&ehci {
	status = "okay";
};

&ohci {
	status = "okay";
};

&ethernet {
	pinctrl-names = "default";
	pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;

	port@5 {
		status = "okay";
		phy-mode = "rgmii";
		mediatek,fixed-link = <1000 1 1 1>;
	};

	mdio-bus {
		status = "okay";

		ethernet-phy@0 {
			reg = <0>;
			phy-mode = "rgmii";
			qca,ar8327-initvals = <
				0x04 0x87300000 /* PORT0 PAD MODE CTRL */
				0x0c 0x00000000 /* PORT6 PAD MODE CTRL */
				0x7c 0x0000007e /* PORT0_STATUS */
				0x80 0x00001200 /* PORT1_STATUS */
				0x84 0x00001200 /* PORT2_STATUS */
				0x88 0x00001200 /* PORT3_STATUS */
				0x8c 0x00001200 /* PORT4_STATUS */
				0x90 0x00001200 /* PORT5_STATUS */
				0x94 0x00000000 /* PORT6_STATUS */
			>;
		};
	};
};

&gsw {
	mediatek,ephy-base = /bits/ 8 <8>;
};

&pcie {
	status = "okay";
};

&pcie0 {
	mt76x0e@0,0 {
		reg = <0x0000 0 0 0 0>;
		nvmem-cells = <&eeprom_config_e08a>, <&macaddr_config_e07e 2>;
		nvmem-cell-names = "eeprom", "mac-address";
	};
};

&state_default {
	gpio {
		groups = "uartf", "i2c";
		function = "gpio";
	};
};