2016-12-02 10:50:26 +00:00
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From fdd5a9166e76db86360c19da7917cd0aab407b85 Mon Sep 17 00:00:00 2001
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2016-04-24 11:03:39 +00:00
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From: Eric Anholt <eric@anholt.net>
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Date: Fri, 12 Feb 2016 14:15:14 -0800
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2016-09-10 12:54:26 +00:00
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Subject: [PATCH] drm/vc4: Bring HDMI up from power off if necessary.
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2016-04-24 11:03:39 +00:00
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If the firmware hadn't brought up HDMI for us, we need to do its
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power-on reset sequence (reset HD and and clear its STANDBY bits,
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reset HDMI, and leave the PHY disabled).
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Signed-off-by: Eric Anholt <eric@anholt.net>
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(cherry picked from commit 851479ad5927b7b1aa141ca9dedb897a7bce2b1d)
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---
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drivers/gpu/drm/vc4/vc4_hdmi.c | 29 ++++++++++++++++++++++++++++-
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drivers/gpu/drm/vc4/vc4_regs.h | 2 ++
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2 files changed, 30 insertions(+), 1 deletion(-)
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
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@@ -497,6 +497,16 @@ static int vc4_hdmi_bind(struct device *
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goto err_put_i2c;
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}
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+ /* This is the rate that is set by the firmware. The number
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+ * needs to be a bit higher than the pixel clock rate
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+ * (generally 148.5Mhz).
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+ */
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+ ret = clk_set_rate(hdmi->hsm_clock, 163682864);
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+ if (ret) {
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+ DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
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+ goto err_unprepare_pix;
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+ }
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+
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ret = clk_prepare_enable(hdmi->hsm_clock);
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if (ret) {
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DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n",
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@@ -518,7 +528,24 @@ static int vc4_hdmi_bind(struct device *
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vc4->hdmi = hdmi;
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/* HDMI core must be enabled. */
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- WARN_ON_ONCE((HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE) == 0);
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+ if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) {
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+ HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST);
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+ udelay(1);
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+ HD_WRITE(VC4_HD_M_CTL, 0);
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+
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+ HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE);
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+
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+ HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL,
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+ VC4_HDMI_SW_RESET_HDMI |
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+ VC4_HDMI_SW_RESET_FORMAT_DETECT);
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+
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+ HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0);
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+
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+ /* PHY should be in reset, like
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+ * vc4_hdmi_encoder_disable() does.
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+ */
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+ HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
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+ }
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drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs,
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DRM_MODE_ENCODER_TMDS);
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--- a/drivers/gpu/drm/vc4/vc4_regs.h
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+++ b/drivers/gpu/drm/vc4/vc4_regs.h
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@@ -456,6 +456,8 @@
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#define VC4_HDMI_TX_PHY_RESET_CTL 0x2c0
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#define VC4_HD_M_CTL 0x00c
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+# define VC4_HD_M_REGISTER_FILE_STANDBY (3 << 6)
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+# define VC4_HD_M_RAM_STANDBY (3 << 4)
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# define VC4_HD_M_SW_RST BIT(2)
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# define VC4_HD_M_ENABLE BIT(0)
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