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118 lines
3.5 KiB
Diff
118 lines
3.5 KiB
Diff
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From 2982f395c9a513b168f1e685588f70013cba2f5f Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
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Date: Mon, 22 Apr 2024 10:15:14 +0300
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Subject: [PATCH 07/15] net: dsa: mt7530: move MT753X_MTRAP operations for
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MT7530
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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On MT7530, the media-independent interfaces of port 5 and 6 are controlled
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by the MT7530_P5_DIS and MT7530_P6_DIS bits of the hardware trap. Deal with
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these bits only when the relevant port is being enabled or disabled. This
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ensures that these ports will be disabled when they are not in use.
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Do not set MT7530_CHG_TRAP on mt7530_setup_port5() as that's already being
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done on mt7530_setup().
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Instead of globally setting MT7530_P5_MAC_SEL, clear it, then set it only
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on the appropriate case.
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If PHY muxing is detected, clear MT7530_P5_DIS before calling
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mt7530_setup_port5().
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Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
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---
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drivers/net/dsa/mt7530.c | 38 +++++++++++++++++++++++++++-----------
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1 file changed, 27 insertions(+), 11 deletions(-)
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--- a/drivers/net/dsa/mt7530.c
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+++ b/drivers/net/dsa/mt7530.c
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@@ -880,8 +880,7 @@ static void mt7530_setup_port5(struct ds
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val = mt7530_read(priv, MT753X_MTRAP);
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- val |= MT7530_CHG_TRAP | MT7530_P5_MAC_SEL | MT7530_P5_DIS;
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- val &= ~MT7530_P5_RGMII_MODE & ~MT7530_P5_PHY0_SEL;
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+ val &= ~MT7530_P5_PHY0_SEL & ~MT7530_P5_MAC_SEL & ~MT7530_P5_RGMII_MODE;
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switch (priv->p5_mode) {
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/* MUX_PHY_P0: P0 -> P5 -> SoC MAC */
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@@ -891,15 +890,13 @@ static void mt7530_setup_port5(struct ds
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/* MUX_PHY_P4: P4 -> P5 -> SoC MAC */
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case MUX_PHY_P4:
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- val &= ~MT7530_P5_MAC_SEL & ~MT7530_P5_DIS;
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-
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/* Setup the MAC by default for the cpu port */
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mt7530_write(priv, MT753X_PMCR_P(5), 0x56300);
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break;
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/* GMAC5: P5 -> SoC MAC or external PHY */
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default:
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- val &= ~MT7530_P5_DIS;
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+ val |= MT7530_P5_MAC_SEL;
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break;
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}
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@@ -1193,6 +1190,14 @@ mt7530_port_enable(struct dsa_switch *ds
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mutex_unlock(&priv->reg_mutex);
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+ if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
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+ return 0;
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+
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+ if (port == 5)
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+ mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS);
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+ else if (port == 6)
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+ mt7530_clear(priv, MT753X_MTRAP, MT7530_P6_DIS);
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+
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return 0;
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}
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@@ -1211,6 +1216,14 @@ mt7530_port_disable(struct dsa_switch *d
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PCR_MATRIX_CLR);
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mutex_unlock(&priv->reg_mutex);
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+
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+ if (priv->id != ID_MT7530 && priv->id != ID_MT7621)
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+ return;
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+
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+ if (port == 5)
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+ mt7530_set(priv, MT753X_MTRAP, MT7530_P5_DIS);
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+ else if (port == 6)
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+ mt7530_set(priv, MT753X_MTRAP, MT7530_P6_DIS);
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}
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static int
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@@ -2401,11 +2414,11 @@ mt7530_setup(struct dsa_switch *ds)
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mt7530_rmw(priv, MT7530_TRGMII_RD(i),
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RD_TAP_MASK, RD_TAP(16));
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- /* Enable port 6 */
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- val = mt7530_read(priv, MT753X_MTRAP);
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- val &= ~MT7530_P6_DIS & ~MT7530_PHY_INDIRECT_ACCESS;
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- val |= MT7530_CHG_TRAP;
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- mt7530_write(priv, MT753X_MTRAP, val);
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+ /* Allow modifying the trap and directly access PHY registers via the
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+ * MDIO bus the switch is on.
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+ */
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+ mt7530_rmw(priv, MT753X_MTRAP, MT7530_CHG_TRAP |
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+ MT7530_PHY_INDIRECT_ACCESS, MT7530_CHG_TRAP);
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if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ)
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mt7530_pll_setup(priv);
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@@ -2488,8 +2501,11 @@ mt7530_setup(struct dsa_switch *ds)
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break;
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}
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- if (priv->p5_mode == MUX_PHY_P0 || priv->p5_mode == MUX_PHY_P4)
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+ if (priv->p5_mode == MUX_PHY_P0 ||
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+ priv->p5_mode == MUX_PHY_P4) {
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+ mt7530_clear(priv, MT753X_MTRAP, MT7530_P5_DIS);
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mt7530_setup_port5(ds, interface);
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+ }
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}
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#ifdef CONFIG_GPIOLIB
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