mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-25 08:21:14 +00:00
42 lines
1.6 KiB
Diff
42 lines
1.6 KiB
Diff
|
From 82b892c3df4893b123681b2ba725c0861e0112a4 Mon Sep 17 00:00:00 2001
|
||
|
|
From: Robin Gong <yibin.gong@nxp.com>
|
||
|
|
Date: Tue, 13 Mar 2018 02:03:09 +0800
|
||
|
|
Subject: [PATCH] MLK-17782 dma: fsl-edma-v3: fix issue reported by Coverity
|
||
|
|
|
||
|
|
Fix below issue reported by Coverity, actually, don't need this
|
||
|
|
condition check here, remove it.
|
||
|
|
|
||
|
|
CID undefined (#1 of 1): Wrong operator used (CONSTANT_EXPRESSION_RESULT)operator_confusion:
|
||
|
|
(16UL /* 1UL << 4 */) | (__u16)(__le16)tcd->csr is always 1/true regardless of the values of its operand.
|
||
|
|
This occurs as the logical first operand of "&&".
|
||
|
|
|
||
|
|
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
|
||
|
|
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
|
||
|
|
(cherry picked from commit ab942110975cadcde57ab1110df03f526bd3fec5)
|
||
|
|
---
|
||
|
|
drivers/dma/fsl-edma-v3.c | 6 ++----
|
||
|
|
1 file changed, 2 insertions(+), 4 deletions(-)
|
||
|
|
|
||
|
|
--- a/drivers/dma/fsl-edma-v3.c
|
||
|
|
+++ b/drivers/dma/fsl-edma-v3.c
|
||
|
|
@@ -1,7 +1,7 @@
|
||
|
|
/*
|
||
|
|
* drivers/dma/fsl-edma3-v3.c
|
||
|
|
*
|
||
|
|
- * Copyright 2017 NXP .
|
||
|
|
+ * Copyright 2017-2018 NXP .
|
||
|
|
*
|
||
|
|
* Driver for the Freescale eDMA engine v3. This driver based on fsl-edma3.c
|
||
|
|
* but changed to meet the IP change on i.MX8QM: every dma channel is specific
|
||
|
|
@@ -451,9 +451,7 @@ static void fsl_edma3_set_tcd_regs(struc
|
||
|
|
writel(le32_to_cpu(tcd->dlast_sga), addr + EDMA_TCD_DLAST_SGA);
|
||
|
|
|
||
|
|
/* Must clear CHa_CSR[DONE] bit before enable TCDa_CSR[ESG] */
|
||
|
|
- if ((EDMA_TCD_CSR_E_SG | le16_to_cpu(tcd->csr)) &&
|
||
|
|
- EDMA_CH_CSR_DONE | readl(addr + EDMA_CH_CSR))
|
||
|
|
- writel(EDMA_CH_CSR_DONE, addr + EDMA_CH_CSR);
|
||
|
|
+ writel(readl(addr + EDMA_CH_CSR), addr + EDMA_CH_CSR);
|
||
|
|
|
||
|
|
writew(le16_to_cpu(tcd->csr), addr + EDMA_TCD_CSR);
|
||
|
|
}
|