2020-09-13 07:06:13 +00:00
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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2020-10-15 15:51:42 +00:00
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/dts-v1/;
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2020-11-04 15:20:17 +00:00
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#define STRINGIZE(s) #s
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#define LAN_LABEL(p, s) STRINGIZE(p ## s)
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#define SWITCH_PORT_LABEL(n) LAN_LABEL(lan, n)
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#define INTERNAL_PHY(n) \
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phy##n: ethernet-phy@##n { \
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reg = <##n>; \
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compatible = "ethernet-phy-ieee802.3-c22"; \
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phy-is-integrated; \
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};
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#define EXTERNAL_PHY(n) \
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phy##n: ethernet-phy@##n { \
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reg = <##n>; \
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compatible = "ethernet-phy-ieee802.3-c22"; \
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};
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#define EXTERNAL_SFP_PHY(n) \
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phy##n: ethernet-phy@##n { \
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compatible = "ethernet-phy-ieee802.3-c22"; \
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sfp; \
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media = "fibre"; \
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reg = <##n>; \
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};
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#define SWITCH_PORT(n, s, m) \
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port@##n { \
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reg = <##n>; \
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label = SWITCH_PORT_LABEL(s) ; \
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phy-handle = <&phy##n>; \
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phy-mode = #m ; \
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};
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2020-12-02 09:41:19 +00:00
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#define SWITCH_SFP_PORT(n, s, m) \
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port@##n { \
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reg = <##n>; \
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label = SWITCH_PORT_LABEL(s) ; \
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phy-handle = <&phy##n>; \
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phy-mode = #m ; \
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fixed-link { \
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speed = <1000>; \
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full-duplex; \
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}; \
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};
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2020-09-13 07:06:13 +00:00
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "realtek,rtl838x-soc";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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frequency = <500000000>;
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cpu@0 {
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compatible = "mips,mips4KEc";
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reg = <0>;
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};
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};
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chosen {
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2021-11-14 18:45:30 +00:00
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bootargs = "console=ttyS0,115200";
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2020-09-13 07:06:13 +00:00
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};
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2021-11-14 18:45:31 +00:00
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lx_clk: lx_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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};
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2020-09-13 07:06:13 +00:00
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cpuintc: cpuintc {
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2021-08-11 11:27:38 +00:00
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compatible = "mti,cpu-interrupt-controller";
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2020-09-13 07:06:13 +00:00
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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2020-11-26 11:02:21 +00:00
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};
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2021-05-06 11:46:42 +00:00
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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2021-08-11 10:06:09 +00:00
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ranges = <0x0 0x18000000 0x10000>;
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2021-05-06 11:46:42 +00:00
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intc: rtlintc@3000 {
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compatible = "realtek,rtl-intc";
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reg = <0x3000 0x20>;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupt-map =
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<31 &cpuintc 2>, /* UART0 */
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<30 &cpuintc 1>, /* UART1 */
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<29 &cpuintc 5>, /* TC0 */
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<28 &cpuintc 1>, /* TC1 */
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<27 &cpuintc 1>, /* OCPTO */
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<26 &cpuintc 1>, /* HLXTO */
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<25 &cpuintc 1>, /* SLXTO */
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<24 &cpuintc 4>, /* NIC */
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<23 &cpuintc 4>, /* GPIO_ABCD */
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<22 &cpuintc 4>, /* GPIO_EFGH */
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<21 &cpuintc 4>, /* RTC */
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<20 &cpuintc 3>, /* SWCORE */
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<19 &cpuintc 4>, /* WDT_IP1 */
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<18 &cpuintc 5>; /* WDT_IP2 */
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};
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2020-09-13 07:06:13 +00:00
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2021-05-06 11:46:42 +00:00
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spi0: spi@1200 {
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compatible = "realtek,rtl8380-spi";
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reg = <0x1200 0x100>;
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2020-09-13 07:06:13 +00:00
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2021-05-06 11:46:42 +00:00
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#address-cells = <1>;
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#size-cells = <0>;
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};
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2020-09-13 07:06:13 +00:00
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2021-05-06 11:46:42 +00:00
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uart0: uart@2000 {
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compatible = "ns16550a";
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reg = <0x2000 0x100>;
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2020-09-13 07:06:13 +00:00
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2021-11-14 18:45:31 +00:00
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clocks = <&lx_clk>;
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2020-11-04 15:53:47 +00:00
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2021-05-06 11:46:42 +00:00
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interrupt-parent = <&intc>;
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interrupts = <31>;
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2020-09-13 07:06:13 +00:00
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2021-05-06 11:46:42 +00:00
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reg-io-width = <1>;
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reg-shift = <2>;
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fifo-size = <1>;
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no-loopback-test;
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};
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2020-09-13 07:06:13 +00:00
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2021-05-06 11:46:42 +00:00
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uart1: uart@2100 {
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pinctrl-names = "default";
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pinctrl-0 = <&enable_uart1>;
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2020-11-26 11:02:21 +00:00
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2021-05-06 11:46:42 +00:00
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compatible = "ns16550a";
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reg = <0x2100 0x100>;
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2020-09-13 07:06:13 +00:00
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2021-11-14 18:45:31 +00:00
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clocks = <&lx_clk>;
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2020-09-13 07:06:13 +00:00
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2021-05-06 11:46:42 +00:00
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interrupt-parent = <&intc>;
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interrupts = <30>;
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2020-09-13 07:06:13 +00:00
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2021-05-06 11:46:42 +00:00
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reg-io-width = <1>;
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reg-shift = <2>;
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fifo-size = <1>;
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no-loopback-test;
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2020-09-13 07:06:13 +00:00
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2021-05-06 11:46:42 +00:00
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status = "disabled";
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};
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2021-11-14 18:45:33 +00:00
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watchdog0: watchdog@3150 {
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compatible = "realtek,rtl8380-wdt";
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reg = <0x3150 0xc>;
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realtek,reset-mode = "soc";
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clocks = <&lx_clk>;
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timeout-sec = <30>;
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interrupt-parent = <&intc>;
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interrupt-names = "phase1", "phase2";
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interrupts = <19>, <18>;
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};
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2021-05-06 11:46:42 +00:00
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gpio0: gpio-controller@3500 {
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compatible = "realtek,rtl8380-gpio", "realtek,otto-gpio";
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reg = <0x3500 0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <24>;
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interrupt-parent = <&intc>;
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interrupts = <23>;
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};
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2020-09-13 07:06:13 +00:00
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};
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2020-11-26 11:02:21 +00:00
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gpio1: rtl8231-gpio {
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compatible = "realtek,rtl8231-gpio";
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#gpio-cells = <2>;
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indirect-access-bus-id = <0>;
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gpio-controller;
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2021-08-11 11:27:38 +00:00
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status = "disabled";
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2020-11-26 11:02:21 +00:00
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};
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2021-08-11 10:06:09 +00:00
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pinmux: pinmux@1b001000 {
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2020-11-26 11:02:21 +00:00
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compatible = "pinctrl-single";
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2021-08-11 10:06:09 +00:00
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reg = <0x1b001000 0x4>;
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2020-11-26 11:02:21 +00:00
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pinctrl-single,bit-per-mux;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x1>;
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#pinctrl-cells = <2>;
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enable_uart1: pinmux_enable_uart1 {
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pinctrl-single,bits = <0x0 0x10 0x10>;
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};
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};
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2021-05-07 03:10:10 +00:00
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/* LED_GLB_CTRL */
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2021-08-11 10:06:09 +00:00
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pinmux_led: pinmux@1b00a000 {
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2021-05-07 03:10:10 +00:00
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compatible = "pinctrl-single";
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2021-08-11 10:06:09 +00:00
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reg = <0x1b00a000 0x4>;
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2021-05-07 03:10:10 +00:00
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pinctrl-single,bit-per-mux;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x1>;
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#pinctrl-cells = <2>;
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/* enable GPIO 0 */
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pinmux_disable_sys_led: disable_sys_led {
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pinctrl-single,bits = <0x0 0x0 0x8000>;
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};
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};
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2021-08-11 10:06:09 +00:00
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ethernet0: ethernet@1b00a300 {
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2020-09-13 07:06:13 +00:00
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compatible = "realtek,rtl838x-eth";
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2021-08-11 10:06:09 +00:00
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reg = <0x1b00a300 0x100>;
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2020-11-26 11:02:21 +00:00
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interrupt-parent = <&intc>;
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2020-09-13 07:06:13 +00:00
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interrupts = <24>;
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#interrupt-cells = <1>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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2021-08-11 10:06:09 +00:00
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switch0: switch@1b000000 {
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2021-08-11 11:27:38 +00:00
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compatible = "realtek,rtl83xx-switch";
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2020-09-13 07:06:13 +00:00
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2021-01-21 13:11:35 +00:00
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interrupt-parent = <&intc>;
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interrupts = <20>;
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2020-09-13 07:06:13 +00:00
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};
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};
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