2020-09-13 07:06:13 +00:00
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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2020-10-15 15:51:42 +00:00
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/dts-v1/;
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2020-09-13 07:06:13 +00:00
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "realtek,rtl838x-soc";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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frequency = <500000000>;
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cpu@0 {
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compatible = "mips,mips4KEc";
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reg = <0>;
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};
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x8000000>;
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};
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chosen {
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bootargs = "console=ttyS0,38400";
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};
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cpuintc: cpuintc {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "rtl838x,icu";
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reg = <0xb8003000 0x20>;
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};
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spi0: spi@b8001200 {
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status = "okay";
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compatible = "realtek,rtl838x-nor";
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reg = <0xb8001200 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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uart0: uart@b8002000 {
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status = "disabled";
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compatible = "ns16550a";
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reg = <0xb8002000 0x100>;
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clock-frequency = <200000000>;
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interrupts = <31>;
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reg-io-width = <1>;
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reg-shift = <2>;
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fifo-size = <1>;
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no-loopback-test;
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};
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uart1: uart@b8002100 {
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status = "okay";
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compatible = "ns16550a";
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reg = <0xb8002100 0x100>;
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clock-frequency = <200000000>;
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interrupt-parent = <&cpuintc>;
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interrupts = <30>;
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reg-io-width = <1>;
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reg-shift = <2>;
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fifo-size = <1>;
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no-loopback-test;
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};
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gpio0: gpio-controller@b8003500 {
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compatible = "realtek,rtl838x-gpio";
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reg = <0xb8003500 0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&cpuintc>;
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interrupts = <23>;
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};
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ethernet0: ethernet@bb00a300 {
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status = "okay";
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compatible = "realtek,rtl838x-eth";
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reg = <0xbb00a300 0x100>;
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interrupt-parent = <&cpuintc>;
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interrupts = <24>;
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#interrupt-cells = <1>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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switch0: switch@bb000000 {
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status = "okay";
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compatible = "realtek,rtl838x-switch";
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};
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};
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