mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-24 07:46:48 +00:00
121 lines
4.1 KiB
Diff
121 lines
4.1 KiB
Diff
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--- a/arch/mips/ath79/common.c
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+++ b/arch/mips/ath79/common.c
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@@ -153,6 +153,24 @@ void ath79_device_reset_clear(u32 mask)
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}
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EXPORT_SYMBOL_GPL(ath79_device_reset_clear);
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+void ath79_device_reset2_clear(u32 mask)
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+{
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+ unsigned long flags;
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+ u32 reg;
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+ u32 t;
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+
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+ if (soc_is_qca955x())
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+ reg = QCA955X_RESET_REG_RESET2_MODULE;
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+ else
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+ panic("Reset register not defined for this SOC");
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+
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+ spin_lock_irqsave(&ath79_device_reset_lock, flags);
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+ t = ath79_reset_rr(reg);
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+ ath79_reset_wr(reg, t & ~mask);
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+ spin_unlock_irqrestore(&ath79_device_reset_lock, flags);
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+}
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+EXPORT_SYMBOL_GPL(ath79_device_reset2_clear);
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+
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u32 ath79_device_reset_get(u32 mask)
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{
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unsigned long flags;
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -411,6 +411,7 @@
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#define QCA955X_PLL_CPU_CONFIG_REG 0x00
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#define QCA955X_PLL_DDR_CONFIG_REG 0x04
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#define QCA955X_PLL_CLK_CTRL_REG 0x08
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+#define QCA955X_PLL_PCIE_CONFIG_REG 0x0c
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#define QCA955X_PLL_ETH_XMII_CONTROL_REG 0x28
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#define QCA955X_PLL_ETH_SGMII_CONTROL_REG 0x48
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#define QCA955X_PLL_ETH_SGMII_SERDES_REG 0x4c
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@@ -565,6 +566,7 @@
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#define QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
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#define QCA955X_RESET_REG_RESET_MODULE 0x1c
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+#define QCA955X_RESET_REG_RESET2_MODULE 0xc4
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#define QCA955X_RESET_REG_BOOTSTRAP 0xb0
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#define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
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--- a/arch/mips/include/asm/mach-ath79/ath79.h
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+++ b/arch/mips/include/asm/mach-ath79/ath79.h
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@@ -178,6 +178,7 @@ static inline u32 ath79_reset_rr(unsigne
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void ath79_device_reset_set(u32 mask);
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void ath79_device_reset_clear(u32 mask);
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+void ath79_device_reset2_clear(u32 mask);
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u32 ath79_device_reset_get(u32 mask);
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void ath79_cpu_irq_init(unsigned irq_wb_chan2, unsigned irq_wb_chan3);
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--- a/arch/mips/pci/pci-ar724x.c
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+++ b/arch/mips/pci/pci-ar724x.c
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@@ -335,18 +335,37 @@ static void ar724x_pci_hw_init(struct ar
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int wait = 0;
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/* deassert PCIe host controller and PCIe PHY reset */
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- ath79_device_reset_clear(AR724X_RESET_PCIE);
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- ath79_device_reset_clear(AR724X_RESET_PCIE_PHY);
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+ if (soc_is_qca955x()) {
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+ ath79_device_reset_clear(QCA955X_RESET_PCIE);
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+ mdelay(10);
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+ ath79_device_reset_clear(QCA955X_RESET_PCIE_PHY);
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+ mdelay(10);
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+ ath79_device_reset2_clear(QCA955X_RESET_PCIE);
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+ mdelay(10);
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+ ath79_device_reset2_clear(QCA955X_RESET_PCIE_PHY);
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+ mdelay(10);
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+ } else {
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+ ath79_device_reset_clear(AR724X_RESET_PCIE);
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+ ath79_device_reset_clear(AR724X_RESET_PCIE_PHY);
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+ }
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/* remove the reset of the PCIE PLL */
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- ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
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- ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;
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- ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
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+ if (!soc_is_qca955x()) {
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+ ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
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+ ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_RESET;
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+ ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
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+ }
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/* deassert bypass for the PCIE PLL */
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- ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
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- ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;
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- ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
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+ if (soc_is_qca955x()) {
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+ ppl = ath79_pll_rr(QCA955X_PLL_PCIE_CONFIG_REG);
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+ ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;
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+ ath79_pll_wr(QCA955X_PLL_PCIE_CONFIG_REG, ppl);
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+ } else {
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+ ppl = ath79_pll_rr(AR724X_PLL_REG_PCIE_CONFIG);
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+ ppl &= ~AR724X_PLL_REG_PCIE_CONFIG_PPL_BYPASS;
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+ ath79_pll_wr(AR724X_PLL_REG_PCIE_CONFIG, ppl);
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+ }
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/* set PCIE Application Control to ready */
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app = __raw_readl(apc->ctrl_base + AR724X_PCI_REG_APP);
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@@ -422,8 +441,14 @@ static int ar724x_pci_probe(struct platf
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* Do the full PCIE Root Complex Initialization Sequence if the PCIe
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* host controller is in reset.
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*/
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- if (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE)
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- ar724x_pci_hw_init(apc);
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+ if (soc_is_qca955x()) {
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+ if (ath79_reset_rr(QCA955X_RESET_REG_RESET_MODULE) & QCA955X_RESET_PCIE ||
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+ ath79_reset_rr(QCA955X_RESET_REG_RESET2_MODULE) & QCA955X_RESET_PCIE)
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+ ar724x_pci_hw_init(apc);
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+ } else {
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+ if (ath79_reset_rr(AR724X_RESET_REG_RESET_MODULE) & AR724X_RESET_PCIE)
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+ ar724x_pci_hw_init(apc);
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+ }
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apc->link_up = ar724x_pci_check_link(apc);
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if (!apc->link_up)
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