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64 lines
2.0 KiB
Diff
64 lines
2.0 KiB
Diff
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From 9344f58d60a0a53ec39e7c5d75021843e859970f Mon Sep 17 00:00:00 2001
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From: Vladimir Oltean <vladimir.oltean@nxp.com>
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Date: Fri, 29 Nov 2019 03:18:32 +0200
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Subject: [PATCH] arm64: dts: fsl: ls1028a: Disable eno3 and make swp5 the
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Felix CPU port
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This patch returns to the switch port setup from BSP 0.2, where the
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switch only had a single Ethernet connection to the CPU, via a tagging
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interface. Choose eno2 for this purpose, as it has higher bandwidth and
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also supports TSN offloads.
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The reason is that the switch is not able to do DSA tags on 2 CPU ports
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at the same time, and it is confusing to have so many ports with no
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clear indication which should be used for what (a "data" port and a
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"control" port).
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We don't revert to the BSP 0.2 RCW configuration, however. The ENETC
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port 3 is still enabled in the RCW, however it is not probed by Linux by
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default, since the large majority of use cases will not need it. For
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those that do (like originating 802.1CB traffic from the CPU), it can be
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enabled back by simply reverting this device tree change.
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Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
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---
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arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 6 ++++--
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1 file changed, 4 insertions(+), 2 deletions(-)
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--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
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@@ -755,7 +755,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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};
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- ethernet@0,2 {
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+ enetc_port2: ethernet@0,2 {
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compatible = "fsl,enetc";
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reg = <0x000200 0 0 0 0>;
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fixed-link {
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@@ -794,6 +794,7 @@
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/* internal to-cpu ports */
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port@4 {
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reg = <4>;
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+ ethernet = <&enetc_port2>;
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phy-mode = "gmii";
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fixed-link {
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@@ -803,7 +804,6 @@
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};
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port@5 {
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reg = <5>;
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- ethernet = <&enetc_port3>;
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phy-mode = "gmii";
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fixed-link {
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@@ -816,6 +816,8 @@
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enetc_port3: ethernet@0,6 {
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compatible = "fsl,enetc";
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reg = <0x000600 0 0 0 0>;
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+ status = "disabled";
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+
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fixed-link {
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speed = <1000>;
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full-duplex;
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