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75 lines
2.8 KiB
Diff
75 lines
2.8 KiB
Diff
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From cd81d3a0695cc54ad6ac0ef4bbb67a7c8f55d592 Mon Sep 17 00:00:00 2001
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From: Niklas Cassel <cassel@kernel.org>
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Date: Thu, 2 May 2024 16:02:32 +0200
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Subject: [PATCH] arm64: dts: rockchip: add rk3588 pcie and php IOMMUs
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The mmu600_pcie is connected with the five PCIe controllers.
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The mmu600_php is connected with the USB3 controller, the GMAC
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controllers, and the SATA controllers.
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See 8.2 Block Diagram, in rk3588 TRM (Technical Reference Manual).
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The IOMMUs are disabled by default, as further patches are needed to
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program the SID/SSIDs in to the IOMMUs.
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iommu: Default domain type: Translated
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iommu: DMA domain TLB invalidation policy: strict mode
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arm-smmu-v3 fc900000.iommu: ias 48-bit, oas 48-bit (features 0x001c1eaf)
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arm-smmu-v3 fc900000.iommu: allocated 65536 entries for cmdq
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arm-smmu-v3 fc900000.iommu: allocated 32768 entries for evtq
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arm-smmu-v3 fc900000.iommu: msi_domain absent - falling back to wired irqs
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Additionally, the IOMMU correctly triggers an IOMMU fault when
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a PCIe device performs a write (since the device hasn't been
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assigned a SID/SSID):
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arm-smmu-v3 fc900000.iommu: event 0x02 received:
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arm-smmu-v3 fc900000.iommu: 0x0000010000000002
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arm-smmu-v3 fc900000.iommu: 0x0000000000000000
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arm-smmu-v3 fc900000.iommu: 0x0000000000000000
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arm-smmu-v3 fc900000.iommu: 0x0000000000000000
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While this doesn't provide much value as is, having the devices as
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disabled in the device tree will allow developers to see that the rk3588
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actually has IOMMUs on the SoC.
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Signed-off-by: Niklas Cassel <cassel@kernel.org>
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Link: https://lore.kernel.org/r/20240502140231.477049-2-cassel@kernel.org
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 24 +++++++++++++++++++++++
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1 file changed, 24 insertions(+)
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--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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@@ -579,6 +579,30 @@
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status = "disabled";
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};
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+ mmu600_pcie: iommu@fc900000 {
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+ compatible = "arm,smmu-v3";
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+ reg = <0x0 0xfc900000 0x0 0x200000>;
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+ interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>,
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+ <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH 0>,
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+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH 0>,
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+ <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>;
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+ interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
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+ #iommu-cells = <1>;
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+ status = "disabled";
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+ };
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+
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+ mmu600_php: iommu@fcb00000 {
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+ compatible = "arm,smmu-v3";
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+ reg = <0x0 0xfcb00000 0x0 0x200000>;
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+ interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>,
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+ <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>,
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+ <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH 0>,
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+ <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH 0>;
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+ interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
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+ #iommu-cells = <1>;
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+ status = "disabled";
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+ };
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+
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pmu1grf: syscon@fd58a000 {
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compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
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reg = <0x0 0xfd58a000 0x0 0x10000>;
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