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40 lines
1.4 KiB
Diff
40 lines
1.4 KiB
Diff
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From 7f75f43fe2159123baa101fcc8c6faa0b0a4c598 Mon Sep 17 00:00:00 2001
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From: Alexander Couzens <lynxis@fe80.eu>
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Date: Sat, 13 Aug 2022 14:48:51 +0200
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Subject: [PATCH 05/10] net: mtk_sgmii: fix powering up the SGMII phy
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There are certain race condition when the SGMII_PHYA_PWD register still
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contains 0x9 which prevents the SGMII from working properly.
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The SGMII still shows link but no traffic can flow.
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Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
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---
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drivers/net/ethernet/mediatek/mtk_sgmii.c | 8 ++------
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1 file changed, 2 insertions(+), 6 deletions(-)
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--- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
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+++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
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@@ -36,9 +36,7 @@ static int mtk_pcs_setup_mode_an(struct
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val |= SGMII_AN_RESTART;
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regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val);
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- regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val);
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- val &= ~SGMII_PHYA_PWD;
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- regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val);
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+ regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0);
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return 0;
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@@ -70,9 +68,7 @@ static int mtk_pcs_setup_mode_force(stru
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regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
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/* Release PHYA power down state */
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- regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val);
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- val &= ~SGMII_PHYA_PWD;
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- regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val);
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+ regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0);
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return 0;
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}
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