2020-04-10 02:47:05 +00:00
|
|
|
From 127b30b66c3b48ee717ed7335987334e8dc769b5 Mon Sep 17 00:00:00 2001
|
|
|
|
|
From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
|
|
|
|
|
Date: Tue, 1 Oct 2019 13:47:11 +0300
|
|
|
|
|
Subject: [PATCH] arm64: dts: ls1028a: fix dwc pci over smmu
|
|
|
|
|
|
|
|
|
|
In order for the dwc controller to work with SMMU it needs the
|
|
|
|
|
bootloader to fixup it's iommu-map property. In the current
|
|
|
|
|
implementation to bootloader will not perform the fixup if the
|
|
|
|
|
property is not already in the device tree with dummy fields.
|
|
|
|
|
Add it to fix DWC PCI over SMMU.
|
|
|
|
|
|
|
|
|
|
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
|
|
|
|
|
---
|
|
|
|
|
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 2 ++
|
|
|
|
|
1 file changed, 2 insertions(+)
|
|
|
|
|
|
|
|
|
|
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
|
|
|
|
|
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
|
2021-10-13 19:14:17 +00:00
|
|
|
@@ -707,6 +707,7 @@
|
2020-04-10 02:47:05 +00:00
|
|
|
#size-cells = <2>;
|
|
|
|
|
device_type = "pci";
|
|
|
|
|
dma-coherent;
|
|
|
|
|
+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
|
|
|
|
|
bus-range = <0x0 0xff>;
|
|
|
|
|
ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */
|
|
|
|
|
0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
2021-10-13 19:14:17 +00:00
|
|
|
@@ -732,6 +733,7 @@
|
2020-04-10 02:47:05 +00:00
|
|
|
#size-cells = <2>;
|
|
|
|
|
device_type = "pci";
|
|
|
|
|
dma-coherent;
|
|
|
|
|
+ iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
|
|
|
|
|
bus-range = <0x0 0xff>;
|
|
|
|
|
ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */
|
|
|
|
|
0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
|
