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64 lines
2.1 KiB
Diff
64 lines
2.1 KiB
Diff
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From 575fc16e92287349f0ffd8399dd9d7e408954cd4 Mon Sep 17 00:00:00 2001
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From: Sandor Yu <Sandor.yu@nxp.com>
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Date: Fri, 29 Nov 2019 15:05:03 +0800
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Subject: [PATCH] Revert "drm/imx/hdp: fix issue with non-SCDC HDMI sinks"
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For HDMI sinks that support HDMI2.0, those video modes have
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listed in hdmi1.4 specification should work in hdmi 1.4.
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Remove the patch, make sure all video modes can work well
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in HDMI2.0 sinks.
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For non-SCDC HDMI sinks issue,
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it will be fixed with another patch.
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This reverts commit 4b6617643f9e3a6f61d42eae39034ddc8d4825af.
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Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
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---
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drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c | 20 ++++++++++----------
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1 file changed, 10 insertions(+), 10 deletions(-)
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--- a/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
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+++ b/drivers/gpu/drm/bridge/cadence/cdns-hdmi-core.c
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@@ -29,17 +29,11 @@
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static void hdmi_sink_config(struct cdns_mhdp_device *mhdp)
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{
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struct drm_scdc *scdc = &mhdp->connector.base.display_info.hdmi.scdc;
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- struct drm_display_info *di = &mhdp->connector.base.display_info;
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- u8 buff = 0;
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-
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- if (scdc->supported || di->color_formats & DRM_COLOR_FORMAT_YCRCB420)
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- mhdp->hdmi.hdmi_type = MODE_HDMI_2_0;
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- else
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- mhdp->hdmi.hdmi_type = MODE_HDMI_1_4;
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+ u8 buff;
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/* check sink support SCDC or not */
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- if (!scdc->supported) {
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- DRM_INFO("Sink does not support SCDC\n");
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+ if (scdc->supported != true) {
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+ DRM_INFO("Sink Not Support SCDC\n");
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return;
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}
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@@ -49,13 +43,19 @@ static void hdmi_sink_config(struct cdns
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* Enable scrambling and TMDS_Bit_Clock_Ratio
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*/
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buff = SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 | SCDC_SCRAMBLING_ENABLE;
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+ mhdp->hdmi.hdmi_type = MODE_HDMI_2_0;
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} else if (scdc->scrambling.low_rates) {
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/*
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* Enable scrambling and HDMI2.0 when scrambling capability of sink
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* be indicated in the HF-VSDB LTE_340Mcsc_scramble bit
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*/
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buff = SCDC_SCRAMBLING_ENABLE;
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- }
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+ mhdp->hdmi.hdmi_type = MODE_HDMI_2_0;
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+ } else {
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+ /* Default work in HDMI1.4 */
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+ buff = 0;
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+ mhdp->hdmi.hdmi_type = MODE_HDMI_1_4;
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+ }
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/* TMDS config */
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cdns_hdmi_scdc_write(mhdp, 0x20, buff);
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