2022-11-03 17:23:44 +00:00
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "mt7621.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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/ {
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compatible = "snr,snr-cpe-me1", "mediatek,mt7621-soc";
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model = "SNR-CPE-ME1";
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aliases {
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label-mac-device = &gmac1;
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led-boot = &led_usb;
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led-failsafe = &led_vpn;
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led-running = &led_green;
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led-upgrade = &led_sys;
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};
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leds {
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compatible = "gpio-leds";
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led_usb: led-0 { // USB Activity
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_USB;
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gpios = <&gpio 13 GPIO_ACTIVE_LOW>; // [JTAG] JTDO
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};
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led_vpn: led-1 { // VPN Activity
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_INDICATOR;
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gpios = <&gpio 16 GPIO_ACTIVE_LOW>; // [JTAG] JTCLK
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};
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led_sys: led-2 { // System config
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_STATUS;
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gpios = <&gpio 3 GPIO_ACTIVE_LOW>; // [I2C] I2C_SD
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panic-indicator;
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};
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led_green: led-3 { // ? LED
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_HEARTBEAT;
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gpios = <&gpio 15 GPIO_ACTIVE_LOW>; // [JTAG] JTMS
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};
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};
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keys {
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compatible = "gpio-keys";
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reset {
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label = "Reset Button";
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gpios = <&gpio 14 GPIO_ACTIVE_LOW>; // [JTAG] JTDI
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linux,code = <KEY_RESTART>;
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};
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};
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reg_usb_vbus: regulator {
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compatible = "regulator-fixed";
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regulator-name = "usb_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio 17 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_3p3v: regulator-3p3v {
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compatible = "regulator-fixed";
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regulator-name = "fixed-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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&gmac0 {
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nvmem-cells = <&macaddr_factory_e000>;
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nvmem-cell-names = "mac-address";
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};
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&gmac1 {
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status = "okay";
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label = "wan";
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phy-handle = <ðphy4>;
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nvmem-cells = <&macaddr_factory_e006>;
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nvmem-cell-names = "mac-address";
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};
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ramips: mt7621-dts: describe switch PHYs and adjust PHY muxing
Currently, the MT7530 DSA subdriver configures the MT7530 switch to provide
direct access to switch PHYs, meaning, the switch PHYs listen on the MDIO
bus the switch listens on. The PHY muxing feature makes use of this.
This is problematic as the PHY may be attached before the switch is
initialised, in which case, the PHY will fail to be attached.
Since commit 91374ba537bd ("net: dsa: mt7530: support OF-based registration
of switch MDIO bus") on mainline Linux, we can describe the switch PHYs on
the MDIO bus of the switch on the device tree.
When the PHY is described this way, the switch will be initialised first,
then the switch MDIO bus will be registered. Only after these steps, the
PHY will be attached.
Describe the switch PHYs on mt7621.dtsi and remove defining the switch PHY
on the SoC's mdio bus node. When the PHY muxing is in use, the interrupts
for the muxed PHY won't work, therefore delete the "interrupts" property on
the devices where the PHY muxing feature is in use.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
2024-04-28 19:52:51 +00:00
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ðphy4 {
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/delete-property/ interrupts;
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2022-11-03 17:23:44 +00:00
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};
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&pcie {
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status = "okay";
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};
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&pcie0 { // MT7603EN
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wifi@0,0 {
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compatible = "mediatek,mt76";
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reg = <0x0000 0 0 0 0>;
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2023-10-02 02:12:02 +00:00
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nvmem-cells = <&eeprom_factory_0>;
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nvmem-cell-names = "eeprom";
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2022-11-03 17:23:44 +00:00
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ieee80211-freq-limit = <2400000 2500000>;
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};
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};
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&pcie1 { // MT7610EN
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wifi@0,0 {
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compatible = "mediatek,mt76";
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reg = <0x0000 0 0 0 0>;
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2023-10-02 02:12:02 +00:00
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nvmem-cells = <&eeprom_factory_8000>;
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nvmem-cell-names = "eeprom";
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2022-11-03 17:23:44 +00:00
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ieee80211-freq-limit = <5000000 6000000>;
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};
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};
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&spi0 {
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status = "okay";
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flash@0 { // GD25Q128CSIG
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <44000000>; // 44 MHz
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "Bootloader";
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reg = <0x0 0x30000>;
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read-only;
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};
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partition@30000 {
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label = "Config";
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reg = <0x30000 0x10000>;
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read-only;
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};
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2024-02-17 14:10:10 +00:00
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partition@40000 {
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2022-11-03 17:23:44 +00:00
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label = "Factory";
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reg = <0x40000 0x10000>;
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2023-10-02 02:12:02 +00:00
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read-only;
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2023-11-07 23:55:58 +00:00
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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2022-11-03 17:23:44 +00:00
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2023-11-07 23:55:58 +00:00
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eeprom_factory_0: eeprom@0 {
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reg = <0x0 0x400>;
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};
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2023-10-02 02:12:02 +00:00
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2023-11-07 23:55:58 +00:00
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eeprom_factory_8000: eeprom@8000 {
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reg = <0x8000 0x200>;
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};
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macaddr_factory_e000: macaddr@e000 {
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reg = <0xe000 0x6>;
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};
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2022-11-03 17:23:44 +00:00
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2023-11-07 23:55:58 +00:00
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macaddr_factory_e006: macaddr@e006 {
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reg = <0xe006 0x6>;
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};
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2022-11-03 17:23:44 +00:00
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};
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};
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partition@50000 {
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compatible = "openwrt,uimage", "denx,uimage";
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label = "firmware";
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reg = <0x50000 0xfb0000>;
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};
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partition@30001 {
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label = "uboot-env";
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reg = <0x30000 0x1000>;
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};
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};
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};
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};
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&state_default {
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gpio {
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groups = "i2c", "jtag";
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function = "gpio";
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};
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};
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&switch0 {
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ports {
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port@0 {
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status = "okay";
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label = "lan4";
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};
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port@1 {
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status = "okay";
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label = "lan3";
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};
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port@2 {
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status = "okay";
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label = "lan2";
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};
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port@3 {
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status = "okay";
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label = "lan1";
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};
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};
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};
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&xhci {
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vbus-supply = <®_usb_vbus>;
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vusb33-supply = <®_3p3v>;
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};
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