openwrt/target/linux/ramips/dts/mt7620a_dlink_dwr-118-a1.dts

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "mt7620a.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/mtd/partitions/uimage.h>
/ {
compatible = "dlink,dwr-118-a1", "ralink,mt7620a-soc";
model = "D-Link DWR-118 A1";
aliases {
led-boot = &led_internet;
led-failsafe = &led_internet;
led-upgrade = &led_internet;
};
keys {
compatible = "gpio-keys";
wps {
label = "wps";
gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
};
reset {
label = "reset";
gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
wan {
function = LED_FUNCTION_WAN;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
};
led_internet: internet {
label = "green:internet";
gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
};
lan {
function = LED_FUNCTION_LAN;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
};
wlan2g {
label = "green:wlan2g";
gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
};
usb {
function = LED_FUNCTION_USB;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
trigger-sources = <&ohci_port1>, <&ehci_port1>;
linux,default-trigger = "usbport";
};
};
gpio_export {
compatible = "gpio-export";
#size-cells = <0>;
usb {
gpio-export,name = "usb";
gpio-export,output = <0>;
gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
};
};
};
&gpio1 {
status = "okay";
};
&gpio2 {
status = "okay";
};
&gpio3 {
status = "okay";
};
&spi0 {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "jboot";
reg = <0x0 0x10000>;
read-only;
};
partition@10000 {
compatible = "openwrt,uimage", "denx,uimage";
openwrt,ih-magic = <IH_MAGIC_OKLI>;
openwrt,offset = <0x10000>;
label = "firmware";
reg = <0x10000 0xfe0000>;
};
partition@ff0000 {
label = "config";
reg = <0xff0000 0x10000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
eeprom_config_e083: eeprom@e083 {
reg = <0xe083 0x200>;
};
macaddr_config_e496: macaddr@e496 {
compatible = "mac-base";
reg = <0xe496 0x6>;
#nvmem-cell-cells = <1>;
};
};
};
};
};
};
&ehci {
status = "okay";
};
&ohci {
status = "okay";
};
&state_default {
default {
groups = "ephy", "uartf", "spi refclk", "wled";
function = "gpio";
};
};
&pcie {
status = "okay";
};
&pcie0 {
wifi@0,0 {
reg = <0x0000 0 0 0 0>;
nvmem-cells = <&eeprom_config_e083>, <&macaddr_config_e496 2>;
nvmem-cell-names = "eeprom", "mac-address";
led {
led-sources = <0>;
led-active-low;
};
};
};
&ethernet {
pinctrl-names = "default";
pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
port@4 {
status = "okay";
phy-handle = <&phy4>;
phy-mode = "rgmii";
};
port@5 {
status = "okay";
phy-handle = <&phy5>;
phy-mode = "rgmii";
};
mdio-bus {
status = "okay";
phy4: ethernet-phy@4 {
reg = <4>;
phy-mode = "rgmii-rxid";
};
phy5: ethernet-phy@5 {
reg = <5>;
phy-mode = "rgmii-rxid";
};
};
};
&gsw {
mediatek,port4-gmac;
mediatek,ephy-base = /bits/ 8 <8>;
};