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76 lines
2.7 KiB
Diff
76 lines
2.7 KiB
Diff
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From 33f393a2a990e16f56931ca708295f31d2b44415 Mon Sep 17 00:00:00 2001
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From: Sebastian Reichel <sebastian.reichel@collabora.com>
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Date: Tue, 9 Apr 2024 00:50:34 +0200
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Subject: [PATCH] arm64: dts: rockchip: add USB3 DRD controllers on rk3588
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Add both USB3 dual-role controllers to the RK3588 devicetree.
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Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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Link: https://lore.kernel.org/r/20240408225109.128953-8-sebastian.reichel@collabora.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/rk3588.dtsi | 20 ++++++++++++++++++++
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arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 22 ++++++++++++++++++++++
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2 files changed, 42 insertions(+)
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--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
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@@ -7,6 +7,26 @@
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#include "rk3588-pinctrl.dtsi"
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/ {
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+ usb_host1_xhci: usb@fc400000 {
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+ compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
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+ reg = <0x0 0xfc400000 0x0 0x400000>;
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+ interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
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+ clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
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+ <&cru ACLK_USB3OTG1>;
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+ clock-names = "ref_clk", "suspend_clk", "bus_clk";
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+ dr_mode = "otg";
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+ phys = <&u2phy1_otg>, <&usbdp_phy1 PHY_TYPE_USB3>;
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+ phy-names = "usb2-phy", "usb3-phy";
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+ phy_type = "utmi_wide";
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+ power-domains = <&power RK3588_PD_USB>;
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+ resets = <&cru SRST_A_USB3OTG1>;
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+ snps,dis_enblslpm_quirk;
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+ snps,dis-u2-freeclk-exists-quirk;
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+ snps,dis-del-phy-power-chg-quirk;
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+ snps,dis-tx-ipgap-linecheck-quirk;
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+ status = "disabled";
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+ };
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+
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pcie30_phy_grf: syscon@fd5b8000 {
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compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
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reg = <0x0 0xfd5b8000 0x0 0x10000>;
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--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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@@ -492,6 +492,28 @@
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};
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};
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+ usb_host0_xhci: usb@fc000000 {
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+ compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
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+ reg = <0x0 0xfc000000 0x0 0x400000>;
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+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
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+ clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
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+ <&cru ACLK_USB3OTG0>;
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+ clock-names = "ref_clk", "suspend_clk", "bus_clk";
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+ dr_mode = "otg";
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+ phys = <&u2phy0_otg>, <&usbdp_phy0 PHY_TYPE_USB3>;
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+ phy-names = "usb2-phy", "usb3-phy";
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+ phy_type = "utmi_wide";
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+ power-domains = <&power RK3588_PD_USB>;
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+ resets = <&cru SRST_A_USB3OTG0>;
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+ snps,dis_enblslpm_quirk;
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+ snps,dis-u1-entry-quirk;
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+ snps,dis-u2-entry-quirk;
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+ snps,dis-u2-freeclk-exists-quirk;
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+ snps,dis-del-phy-power-chg-quirk;
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+ snps,dis-tx-ipgap-linecheck-quirk;
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+ status = "disabled";
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+ };
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+
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usb_host0_ehci: usb@fc800000 {
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compatible = "rockchip,rk3588-ehci", "generic-ehci";
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reg = <0x0 0xfc800000 0x0 0x40000>;
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