mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-23 15:32:33 +00:00
51 lines
2.0 KiB
Diff
51 lines
2.0 KiB
Diff
|
From c5a10c542853662bf85884aecee1c086ecec9acf Mon Sep 17 00:00:00 2001
|
||
|
|
From: Shengjiu Wang <shengjiu.wang@freescale.com>
|
||
|
|
Date: Mon, 5 Jun 2017 11:37:57 +0800
|
||
|
|
Subject: [PATCH] MLK-15003-2: Document: fsl_edma_v3: update document
|
||
|
|
|
||
|
|
update fsl_edma_v3 document for #dma-cell is changed
|
||
|
|
one more cell is added, which is for local/remote access.
|
||
|
|
|
||
|
|
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
|
||
|
|
(cherry picked from commit 65543fb7fefbdb7df4cb60931a88f61507c5073f)
|
||
|
|
---
|
||
|
|
Documentation/devicetree/bindings/dma/fsl-edma-v3.txt | 10 ++++++----
|
||
|
|
1 file changed, 6 insertions(+), 4 deletions(-)
|
||
|
|
|
||
|
|
--- a/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt
|
||
|
|
+++ b/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt
|
||
|
|
@@ -14,11 +14,13 @@ Required properties:
|
||
|
|
- interrupts : A list of interrupt-specifiers, each channel has one interrupt.
|
||
|
|
- interrupt-names : Should contain:
|
||
|
|
"edma-chan12-tx" - the channel12 transmission interrupt
|
||
|
|
-- #dma-cells : Must be <3>.
|
||
|
|
+- #dma-cells : Must be <4>.
|
||
|
|
The 1st cell specifies the channel ID.
|
||
|
|
The 2nd cell specifies the channel priority.
|
||
|
|
The 3rd cell specifies the channel type like for transmit or receive:
|
||
|
|
0: transmit, 1: receive.
|
||
|
|
+ The 4th cell specifies the local access or remote access:
|
||
|
|
+ 0: local, 1: remote.
|
||
|
|
See the SoC's reference manual for all the supported request sources.
|
||
|
|
- dma-channels : Number of channels supported by the controller
|
||
|
|
|
||
|
|
@@ -29,7 +31,7 @@ edma0: dma-controller@40018000 {
|
||
|
|
<0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART0 tx */
|
||
|
|
<0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */
|
||
|
|
<0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART1 tx */
|
||
|
|
- #dma-cells = <3>;
|
||
|
|
+ #dma-cells = <4>;
|
||
|
|
dma-channels = <4>;
|
||
|
|
interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
@@ -58,7 +60,7 @@ lpuart1: serial@5a070000 {
|
||
|
|
assigned-clock-rates = <80000000>;
|
||
|
|
power-domains = <&pd_dma_lpuart1>;
|
||
|
|
dma-names = "tx","rx";
|
||
|
|
- dmas = <&edma0 15 0 0>,
|
||
|
|
- <&edma0 14 0 1>;
|
||
|
|
+ dmas = <&edma0 15 0 0 0>,
|
||
|
|
+ <&edma0 14 0 1 0>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|