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86 lines
3.0 KiB
Diff
86 lines
3.0 KiB
Diff
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From dae2475df84cd77c6f7245984869897c0eb0f84e Mon Sep 17 00:00:00 2001
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From: Wen He <wen.he_1@nxp.com>
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Date: Tue, 10 Sep 2019 15:01:00 +0800
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Subject: [PATCH] drm/arm/mali-dp: Add display QoS interface configuration for
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Mali DP500
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Configure the display Quality of service (QoS) levels priority if the
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optional property node "arm,malidp-aqros-value" is defined in DTS file.
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QoS signaling using AQROS and AWQOS AXI interface signals, the AQROS is
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driven from the "RQOS" register, so needed to program the RQOS register
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to avoid the high resolutions flicker issue on the LS1028A platform.
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Signed-off-by: Wen He <wen.he_1@nxp.com>
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---
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drivers/gpu/drm/arm/malidp_drv.c | 6 ++++++
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drivers/gpu/drm/arm/malidp_hw.c | 9 +++++++++
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drivers/gpu/drm/arm/malidp_hw.h | 3 +++
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drivers/gpu/drm/arm/malidp_regs.h | 10 ++++++++++
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4 files changed, 28 insertions(+)
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--- a/drivers/gpu/drm/arm/malidp_drv.c
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+++ b/drivers/gpu/drm/arm/malidp_drv.c
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@@ -817,6 +817,12 @@ static int malidp_bind(struct device *de
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malidp->core_id = version;
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+ ret = of_property_read_u32(dev->of_node,
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+ "arm,malidp-arqos-value",
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+ &hwdev->arqos_value);
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+ if (ret)
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+ hwdev->arqos_value = 0x0;
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+
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/* set the number of lines used for output of RGB data */
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ret = of_property_read_u8_array(dev->of_node,
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"arm,malidp-output-port-lines",
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--- a/drivers/gpu/drm/arm/malidp_hw.c
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+++ b/drivers/gpu/drm/arm/malidp_hw.c
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@@ -379,6 +379,15 @@ static void malidp500_modeset(struct mal
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malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
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else
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malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
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+
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+ /*
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+ * Program the RQoS register to avoid high resolutions flicker
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+ * issue on the LS1028A.
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+ */
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+ if (hwdev->arqos_value) {
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+ val = hwdev->arqos_value;
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+ malidp_hw_setbits(hwdev, val, MALIDP500_RQOS_QUALITY);
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+ }
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}
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int malidp_format_get_bpp(u32 fmt)
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--- a/drivers/gpu/drm/arm/malidp_hw.h
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+++ b/drivers/gpu/drm/arm/malidp_hw.h
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@@ -251,6 +251,9 @@ struct malidp_hw_device {
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/* size of memory used for rotating layers, up to two banks available */
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u32 rotation_memory[2];
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+
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+ /* priority level of RQOS register used for driven the ARQOS signal */
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+ u32 arqos_value;
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};
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static inline u32 malidp_hw_read(struct malidp_hw_device *hwdev, u32 reg)
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--- a/drivers/gpu/drm/arm/malidp_regs.h
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+++ b/drivers/gpu/drm/arm/malidp_regs.h
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@@ -210,6 +210,16 @@
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#define MALIDP500_CONFIG_VALID 0x00f00
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#define MALIDP500_CONFIG_ID 0x00fd4
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+/*
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+ * The quality of service (QoS) register on the DP500. RQOS register values
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+ * are driven by the ARQOS signal, using AXI transacations, dependent on the
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+ * FIFO input level.
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+ * The RQOS register can also set QoS levels for:
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+ * - RED_ARQOS @ A 4-bit signal value for close to underflow conditions
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+ * - GREEN_ARQOS @ A 4-bit signal value for normal conditions
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+ */
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+#define MALIDP500_RQOS_QUALITY 0x00500
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+
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/* register offsets and bits specific to DP550/DP650 */
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#define MALIDP550_ADDR_SPACE_SIZE 0x10000
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#define MALIDP550_DE_CONTROL 0x00010
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