2023-10-14 17:36:38 +00:00
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From e4d7544ce092807e8c5aeb618cec30e2eb9b40c2 Mon Sep 17 00:00:00 2001
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From: Mantas Pucka <mantas@8devices.com>
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Date: Mon, 24 Apr 2023 15:13:32 +0300
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Subject: [PATCH 3/3] arm64: dts: qcom: ipq6018: add SDHCI node
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IPQ6018 has one SD/eMMC controller, add node for it.
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Signed-off-by: Mantas Pucka <mantas@8devices.com>
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Tested-by: Robert Marko <robimarko@gmail.com>
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---
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arch/arm64/boot/dts/qcom/ipq6018.dtsi | 23 +++++++++++++++++++++++
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1 file changed, 23 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
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2024-03-22 10:08:54 +00:00
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@@ -470,6 +470,29 @@
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2024-01-15 15:28:13 +00:00
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};
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2023-10-14 17:36:38 +00:00
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};
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+ sdhc_1: mmc@7804000 {
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+ compatible = "qcom,ipq6018-sdhci", "qcom,sdhci-msm-v5";
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+ reg = <0x0 0x07804000 0x0 0x1000>,
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+ <0x0 0x07805000 0x0 0x1000>,
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+ <0x0 0x07808000 0x0 0x2000>;
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+ reg-names = "hc", "cqhci", "ice";
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+
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+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "hc_irq", "pwr_irq";
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+
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+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
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+ <&gcc GCC_SDCC1_APPS_CLK>,
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+ <&xo>,
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+ <&gcc GCC_SDCC1_ICE_CORE_CLK>;
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+ clock-names = "iface", "core", "xo", "ice";
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+
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+ resets = <&gcc GCC_SDCC1_BCR>;
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+ supports-cqe;
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+ bus-width = <8>;
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+ status = "disabled";
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+ };
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+
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blsp_dma: dma-controller@7884000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x0 0x07884000 0x0 0x2b000>;
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