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52 lines
1.7 KiB
Diff
52 lines
1.7 KiB
Diff
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From 11d28971aaaf5de6f50790fb21f1113fee21d320 Mon Sep 17 00:00:00 2001
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From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Date: Mon, 19 Feb 2024 22:46:25 +0200
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Subject: [PATCH] arm64: dts: rockchip: Add HDMI0 PHY to rk3588
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Add DT nodes for HDMI0 PHY and related syscon found on RK3588 SoC.
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Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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Link: https://lore.kernel.org/r/20240219204626.284399-1-cristian.ciocaltea@collabora.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 21 +++++++++++++++++++++
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1 file changed, 21 insertions(+)
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--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
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@@ -586,6 +586,11 @@
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};
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};
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+ hdptxphy0_grf: syscon@fd5e0000 {
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+ compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
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+ reg = <0x0 0xfd5e0000 0x0 0x100>;
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+ };
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+
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ioc: syscon@fd5f0000 {
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compatible = "rockchip,rk3588-ioc", "syscon";
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reg = <0x0 0xfd5f0000 0x0 0x10000>;
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@@ -2358,6 +2363,22 @@
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#dma-cells = <1>;
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};
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+ hdptxphy_hdmi0: phy@fed60000 {
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+ compatible = "rockchip,rk3588-hdptx-phy";
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+ reg = <0x0 0xfed60000 0x0 0x2000>;
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+ clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>;
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+ clock-names = "ref", "apb";
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+ #phy-cells = <0>;
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+ resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>,
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+ <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>,
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+ <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>,
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+ <&cru SRST_HDPTX0_LCPLL>;
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+ reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
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+ "lcpll";
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+ rockchip,grf = <&hdptxphy0_grf>;
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+ status = "disabled";
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+ };
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+
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combphy0_ps: phy@fee00000 {
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compatible = "rockchip,rk3588-naneng-combphy";
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reg = <0x0 0xfee00000 0x0 0x100>;
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